dmaengine: Add Synopsys eDMA IP PCIe glue-logic
Synopsys eDMA IP is normally distributed along with Synopsys PCIe EndPoint IP (depends of the use and licensing agreement). This IP requires some basic configurations, such as: - eDMA registers BAR - eDMA registers offset - eDMA registers size - eDMA linked list memory BAR - eDMA linked list memory offset - eDMA linked list memory size - eDMA data memory BAR - eDMA data memory offset - eDMA data memory size - eDMA version - eDMA mode - IRQs available for eDMA As a working example, PCIe glue-logic will attach to a Synopsys PCIe EndPoint IP prototype kit (Vendor ID = 0x16c3, Device ID = 0xedda), which has built-in an eDMA IP with this default configuration: - eDMA registers BAR = 0 - eDMA registers offset = 0x00001000 (4 Kbytes) - eDMA registers size = 0x00002000 (8 Kbytes) - eDMA linked list memory BAR = 2 - eDMA linked list memory offset = 0x00000000 (0 Kbytes) - eDMA linked list memory size = 0x00800000 (8 Mbytes) - eDMA data memory BAR = 2 - eDMA data memory offset = 0x00800000 (8 Mbytes) - eDMA data memory size = 0x03800000 (56 Mbytes) - eDMA version = 0 - eDMA mode = EDMA_MODE_UNROLL - IRQs = 1 This driver can be compile as built-in or external module in kernel. To enable this driver just select DW_EDMA_PCIE option in kernel configuration, however it requires and selects automatically DW_EDMA option too. Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Cc: Vinod Koul <vkoul@kernel.org> Cc: Dan Williams <dan.j.williams@intel.com> Cc: Russell King <rmk+kernel@armlinux.org.uk> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Joao Pinto <jpinto@synopsys.com> Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Gustavo Pimentel
Vinod Koul
parent
1f418f4650
commit
41aaff2a2a
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@ -7,3 +7,12 @@ config DW_EDMA
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help
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Support the Synopsys DesignWare eDMA controller, normally
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implemented on endpoints SoCs.
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config DW_EDMA_PCIE
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tristate "Synopsys DesignWare eDMA PCIe driver"
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depends on PCI && PCI_MSI
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select DW_EDMA
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help
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Provides a glue-logic between the Synopsys DesignWare
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eDMA controller and an endpoint PCIe device. This also serves
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as a reference design to whom desires to use this IP.
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@ -4,3 +4,4 @@ obj-$(CONFIG_DW_EDMA) += dw-edma.o
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dw-edma-$(CONFIG_DEBUG_FS) := dw-edma-v0-debugfs.o
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dw-edma-objs := dw-edma-core.o \
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dw-edma-v0-core.o $(dw-edma-y)
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obj-$(CONFIG_DW_EDMA_PCIE) += dw-edma-pcie.o
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@ -0,0 +1,229 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
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* Synopsys DesignWare eDMA PCIe driver
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*
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* Author: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/device.h>
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#include <linux/dma/edma.h>
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#include <linux/pci-epf.h>
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#include <linux/msi.h>
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#include "dw-edma-core.h"
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struct dw_edma_pcie_data {
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/* eDMA registers location */
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enum pci_barno rg_bar;
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off_t rg_off;
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size_t rg_sz;
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/* eDMA memory linked list location */
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enum pci_barno ll_bar;
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off_t ll_off;
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size_t ll_sz;
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/* eDMA memory data location */
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enum pci_barno dt_bar;
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off_t dt_off;
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size_t dt_sz;
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/* Other */
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u32 version;
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enum dw_edma_mode mode;
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u8 irqs;
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};
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static const struct dw_edma_pcie_data snps_edda_data = {
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/* eDMA registers location */
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.rg_bar = BAR_0,
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.rg_off = 0x00001000, /* 4 Kbytes */
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.rg_sz = 0x00002000, /* 8 Kbytes */
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/* eDMA memory linked list location */
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.ll_bar = BAR_2,
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.ll_off = 0x00000000, /* 0 Kbytes */
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.ll_sz = 0x00800000, /* 8 Mbytes */
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/* eDMA memory data location */
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.dt_bar = BAR_2,
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.dt_off = 0x00800000, /* 8 Mbytes */
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.dt_sz = 0x03800000, /* 56 Mbytes */
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/* Other */
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.version = 0,
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.mode = EDMA_MODE_UNROLL,
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.irqs = 1,
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};
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static int dw_edma_pcie_probe(struct pci_dev *pdev,
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const struct pci_device_id *pid)
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{
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const struct dw_edma_pcie_data *pdata = (void *)pid->driver_data;
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struct device *dev = &pdev->dev;
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struct dw_edma_chip *chip;
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int err, nr_irqs;
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struct dw_edma *dw;
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/* Enable PCI device */
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err = pcim_enable_device(pdev);
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if (err) {
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pci_err(pdev, "enabling device failed\n");
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return err;
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}
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/* Mapping PCI BAR regions */
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err = pcim_iomap_regions(pdev, BIT(pdata->rg_bar) |
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BIT(pdata->ll_bar) |
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BIT(pdata->dt_bar),
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pci_name(pdev));
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if (err) {
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pci_err(pdev, "eDMA BAR I/O remapping failed\n");
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return err;
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}
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pci_set_master(pdev);
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/* DMA configuration */
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err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
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if (!err) {
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err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
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if (err) {
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pci_err(pdev, "consistent DMA mask 64 set failed\n");
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return err;
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}
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} else {
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pci_err(pdev, "DMA mask 64 set failed\n");
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err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
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if (err) {
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pci_err(pdev, "DMA mask 32 set failed\n");
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return err;
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}
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err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
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if (err) {
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pci_err(pdev, "consistent DMA mask 32 set failed\n");
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return err;
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}
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}
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/* Data structure allocation */
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chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
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if (!chip)
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return -ENOMEM;
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dw = devm_kzalloc(dev, sizeof(*dw), GFP_KERNEL);
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if (!dw)
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return -ENOMEM;
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/* IRQs allocation */
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nr_irqs = pci_alloc_irq_vectors(pdev, 1, pdata->irqs,
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PCI_IRQ_MSI | PCI_IRQ_MSIX);
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if (nr_irqs < 1) {
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pci_err(pdev, "fail to alloc IRQ vector (number of IRQs=%u)\n",
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nr_irqs);
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return -EPERM;
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}
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/* Data structure initialization */
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chip->dw = dw;
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chip->dev = dev;
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chip->id = pdev->devfn;
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chip->irq = pdev->irq;
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dw->rg_region.vaddr = (dma_addr_t)pcim_iomap_table(pdev)[pdata->rg_bar];
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dw->rg_region.vaddr += pdata->rg_off;
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dw->rg_region.paddr = pdev->resource[pdata->rg_bar].start;
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dw->rg_region.paddr += pdata->rg_off;
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dw->rg_region.sz = pdata->rg_sz;
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dw->ll_region.vaddr = (dma_addr_t)pcim_iomap_table(pdev)[pdata->ll_bar];
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dw->ll_region.vaddr += pdata->ll_off;
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dw->ll_region.paddr = pdev->resource[pdata->ll_bar].start;
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dw->ll_region.paddr += pdata->ll_off;
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dw->ll_region.sz = pdata->ll_sz;
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dw->dt_region.vaddr = (dma_addr_t)pcim_iomap_table(pdev)[pdata->dt_bar];
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dw->dt_region.vaddr += pdata->dt_off;
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dw->dt_region.paddr = pdev->resource[pdata->dt_bar].start;
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dw->dt_region.paddr += pdata->dt_off;
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dw->dt_region.sz = pdata->dt_sz;
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dw->version = pdata->version;
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dw->mode = pdata->mode;
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dw->nr_irqs = nr_irqs;
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/* Debug info */
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pci_dbg(pdev, "Version:\t%u\n", dw->version);
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pci_dbg(pdev, "Mode:\t%s\n",
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dw->mode == EDMA_MODE_LEGACY ? "Legacy" : "Unroll");
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pci_dbg(pdev, "Registers:\tBAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%pa, p=%pa)\n",
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pdata->rg_bar, pdata->rg_off, pdata->rg_sz,
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&dw->rg_region.vaddr, &dw->rg_region.paddr);
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pci_dbg(pdev, "L. List:\tBAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%pa, p=%pa)\n",
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pdata->ll_bar, pdata->ll_off, pdata->ll_sz,
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&dw->ll_region.vaddr, &dw->ll_region.paddr);
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pci_dbg(pdev, "Data:\tBAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%pa, p=%pa)\n",
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pdata->dt_bar, pdata->dt_off, pdata->dt_sz,
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&dw->dt_region.vaddr, &dw->dt_region.paddr);
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pci_dbg(pdev, "Nr. IRQs:\t%u\n", dw->nr_irqs);
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/* Validating if PCI interrupts were enabled */
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if (!pci_dev_msi_enabled(pdev)) {
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pci_err(pdev, "enable interrupt failed\n");
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return -EPERM;
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}
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dw->irq = devm_kcalloc(dev, nr_irqs, sizeof(*dw->irq), GFP_KERNEL);
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if (!dw->irq)
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return -ENOMEM;
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/* Starting eDMA driver */
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err = dw_edma_probe(chip);
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if (err) {
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pci_err(pdev, "eDMA probe failed\n");
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return err;
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}
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/* Saving data structure reference */
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pci_set_drvdata(pdev, chip);
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return 0;
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}
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static void dw_edma_pcie_remove(struct pci_dev *pdev)
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{
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struct dw_edma_chip *chip = pci_get_drvdata(pdev);
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int err;
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/* Stopping eDMA driver */
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err = dw_edma_remove(chip);
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if (err)
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pci_warn(pdev, "can't remove device properly: %d\n", err);
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/* Freeing IRQs */
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pci_free_irq_vectors(pdev);
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}
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static const struct pci_device_id dw_edma_pcie_id_table[] = {
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{ PCI_DEVICE_DATA(SYNOPSYS, EDDA, &snps_edda_data) },
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{ }
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};
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MODULE_DEVICE_TABLE(pci, dw_edma_pcie_id_table);
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static struct pci_driver dw_edma_pcie_driver = {
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.name = "dw-edma-pcie",
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.id_table = dw_edma_pcie_id_table,
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.probe = dw_edma_pcie_probe,
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.remove = dw_edma_pcie_remove,
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};
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module_pci_driver(dw_edma_pcie_driver);
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("Synopsys DesignWare eDMA PCIe driver");
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MODULE_AUTHOR("Gustavo Pimentel <gustavo.pimentel@synopsys.com>");
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