Merge branch 'clk-fixes' into clk-next
* clk-fixes: clk: sunxi: pll2: Fix clock running too fast clk: scpi: add missing of_node_put clk: qoriq: fix memory leak imx/clk-pllv2: fix wrong do_div() usage imx/clk-pllv1: fix wrong do_div() usage clk: mmp: add linux/clk.h includes clk: ti: drop locking code from mux/divider drivers clk: ti816x: Add missing dmtimer clkdev entries clk: ti: fapll: fix wrong do_div() usage clk: ti: clkt_dpll: fix wrong do_div() usage clk: gpio: Get parent clk names in of_gpio_clk_setup()
This commit is contained in:
Stephen Boyd
commit
41cabbc24d
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@ -209,6 +209,8 @@ EXPORT_SYMBOL_GPL(clk_register_gpio_mux);
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struct clk_gpio_delayed_register_data {
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const char *gpio_name;
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int num_parents;
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const char **parent_names;
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struct device_node *node;
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struct mutex lock;
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struct clk *clk;
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@ -222,8 +224,6 @@ static struct clk *of_clk_gpio_delayed_register_get(
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{
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struct clk_gpio_delayed_register_data *data = _data;
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struct clk *clk;
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const char **parent_names;
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int i, num_parents;
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int gpio;
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enum of_gpio_flags of_flags;
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@ -248,26 +248,14 @@ static struct clk *of_clk_gpio_delayed_register_get(
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return ERR_PTR(gpio);
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}
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num_parents = of_clk_get_parent_count(data->node);
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parent_names = kcalloc(num_parents, sizeof(char *), GFP_KERNEL);
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if (!parent_names) {
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clk = ERR_PTR(-ENOMEM);
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goto out;
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}
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for (i = 0; i < num_parents; i++)
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parent_names[i] = of_clk_get_parent_name(data->node, i);
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clk = data->clk_register_get(data->node->name, parent_names,
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num_parents, gpio, of_flags & OF_GPIO_ACTIVE_LOW);
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clk = data->clk_register_get(data->node->name, data->parent_names,
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data->num_parents, gpio, of_flags & OF_GPIO_ACTIVE_LOW);
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if (IS_ERR(clk))
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goto out;
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data->clk = clk;
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out:
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mutex_unlock(&data->lock);
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kfree(parent_names);
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return clk;
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}
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@ -296,11 +284,24 @@ static void __init of_gpio_clk_setup(struct device_node *node,
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unsigned gpio, bool active_low))
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{
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struct clk_gpio_delayed_register_data *data;
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const char **parent_names;
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int i, num_parents;
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data = kzalloc(sizeof(*data), GFP_KERNEL);
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if (!data)
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return;
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num_parents = of_clk_get_parent_count(node);
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parent_names = kcalloc(num_parents, sizeof(char *), GFP_KERNEL);
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if (!parent_names)
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return;
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for (i = 0; i < num_parents; i++)
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parent_names[i] = of_clk_get_parent_name(node, i);
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data->num_parents = num_parents;
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data->parent_names = parent_names;
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data->node = node;
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data->gpio_name = gpio_name;
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data->clk_register_get = clk_register_get;
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@ -778,8 +778,10 @@ static struct clk * __init create_one_cmux(struct clockgen *cg, int idx)
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*/
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clksel = (cg_in(cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT;
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div = get_pll_div(cg, hwc, clksel);
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if (!div)
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if (!div) {
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kfree(hwc);
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return NULL;
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}
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pct80_rate = clk_get_rate(div->clk);
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pct80_rate *= 8;
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@ -292,6 +292,7 @@ static int scpi_clocks_probe(struct platform_device *pdev)
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ret = scpi_clk_add(dev, child, match);
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if (ret) {
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scpi_clocks_remove(pdev);
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of_node_put(child);
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return ret;
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}
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}
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@ -52,7 +52,7 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_pllv1 *pll = to_clk_pllv1(hw);
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long long ll;
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unsigned long long ull;
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int mfn_abs;
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unsigned int mfi, mfn, mfd, pd;
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u32 reg;
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@ -94,16 +94,16 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
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rate = parent_rate * 2;
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rate /= pd + 1;
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ll = (unsigned long long)rate * mfn_abs;
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ull = (unsigned long long)rate * mfn_abs;
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do_div(ll, mfd + 1);
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do_div(ull, mfd + 1);
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if (mfn_is_negative(pll, mfn))
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ll = -ll;
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ull = (rate * mfi) - ull;
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else
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ull = (rate * mfi) + ull;
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ll = (rate * mfi) + ll;
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return ll;
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return ull;
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}
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static struct clk_ops clk_pllv1_ops = {
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@ -79,7 +79,7 @@ static unsigned long __clk_pllv2_recalc_rate(unsigned long parent_rate,
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{
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long mfi, mfn, mfd, pdf, ref_clk;
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unsigned long dbl;
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s64 temp;
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u64 temp;
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dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN;
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@ -98,8 +98,9 @@ static unsigned long __clk_pllv2_recalc_rate(unsigned long parent_rate,
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temp = (u64) ref_clk * abs(mfn);
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do_div(temp, mfd + 1);
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if (mfn < 0)
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temp = -temp;
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temp = (ref_clk * mfi) + temp;
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temp = (ref_clk * mfi) - temp;
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else
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temp = (ref_clk * mfi) + temp;
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return temp;
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}
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@ -126,7 +127,7 @@ static int __clk_pllv2_set_rate(unsigned long rate, unsigned long parent_rate,
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{
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u32 reg;
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long mfi, pdf, mfn, mfd = 999999;
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s64 temp64;
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u64 temp64;
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unsigned long quad_parent_rate;
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quad_parent_rate = 4 * parent_rate;
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@ -9,6 +9,7 @@
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/spinlock.h>
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@ -9,6 +9,7 @@
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/spinlock.h>
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@ -9,6 +9,7 @@
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/spinlock.h>
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@ -41,15 +41,10 @@
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#define SUN4I_PLL2_OUTPUTS 4
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struct sun4i_pll2_data {
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u32 post_div_offset;
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u32 pre_div_flags;
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};
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static DEFINE_SPINLOCK(sun4i_a10_pll2_lock);
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static void __init sun4i_pll2_setup(struct device_node *node,
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struct sun4i_pll2_data *data)
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int post_div_offset)
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{
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const char *clk_name = node->name, *parent;
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struct clk **clks, *base_clk, *prediv_clk;
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@ -76,7 +71,7 @@ static void __init sun4i_pll2_setup(struct device_node *node,
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parent, 0, reg,
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SUN4I_PLL2_PRE_DIV_SHIFT,
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SUN4I_PLL2_PRE_DIV_WIDTH,
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data->pre_div_flags,
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CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
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&sun4i_a10_pll2_lock);
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if (!prediv_clk) {
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pr_err("Couldn't register the prediv clock\n");
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@ -127,7 +122,7 @@ static void __init sun4i_pll2_setup(struct device_node *node,
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*/
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val = readl(reg);
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val &= ~(SUN4I_PLL2_POST_DIV_MASK << SUN4I_PLL2_POST_DIV_SHIFT);
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val |= (SUN4I_PLL2_POST_DIV_VALUE - data->post_div_offset) << SUN4I_PLL2_POST_DIV_SHIFT;
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val |= (SUN4I_PLL2_POST_DIV_VALUE - post_div_offset) << SUN4I_PLL2_POST_DIV_SHIFT;
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writel(val, reg);
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of_property_read_string_index(node, "clock-output-names",
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@ -191,25 +186,17 @@ static void __init sun4i_pll2_setup(struct device_node *node,
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iounmap(reg);
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}
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static struct sun4i_pll2_data sun4i_a10_pll2_data = {
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.pre_div_flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
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};
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static void __init sun4i_a10_pll2_setup(struct device_node *node)
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{
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sun4i_pll2_setup(node, &sun4i_a10_pll2_data);
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sun4i_pll2_setup(node, 0);
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}
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CLK_OF_DECLARE(sun4i_a10_pll2, "allwinner,sun4i-a10-pll2-clk",
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sun4i_a10_pll2_setup);
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static struct sun4i_pll2_data sun5i_a13_pll2_data = {
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.post_div_offset = 1,
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};
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static void __init sun5i_a13_pll2_setup(struct device_node *node)
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{
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sun4i_pll2_setup(node, &sun5i_a13_pll2_data);
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sun4i_pll2_setup(node, 1);
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}
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CLK_OF_DECLARE(sun5i_a13_pll2, "allwinner,sun5i-a13-pll2-clk",
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@ -20,6 +20,8 @@ static struct ti_dt_clk dm816x_clks[] = {
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DT_CLK(NULL, "sys_clkin", "sys_clkin_ck"),
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DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
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DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"),
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DT_CLK(NULL, "timer_32k_ck", "sysclk18_ck"),
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DT_CLK(NULL, "timer_ext_ck", "tclkin_ck"),
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DT_CLK(NULL, "mpu_ck", "mpu_ck"),
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DT_CLK(NULL, "timer1_fck", "timer1_fck"),
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DT_CLK(NULL, "timer2_fck", "timer2_fck"),
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@ -240,7 +240,7 @@ u8 omap2_init_dpll_parent(struct clk_hw *hw)
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*/
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unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
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{
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long long dpll_clk;
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u64 dpll_clk;
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u32 dpll_mult, dpll_div, v;
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struct dpll_data *dd;
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@ -262,7 +262,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
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dpll_div = v & dd->div1_mask;
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dpll_div >>= __ffs(dd->div1_mask);
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dpll_clk = (long long)clk_get_rate(dd->clk_ref) * dpll_mult;
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dpll_clk = (u64)clk_get_rate(dd->clk_ref) * dpll_mult;
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do_div(dpll_clk, dpll_div + 1);
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return dpll_clk;
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@ -214,7 +214,6 @@ static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
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{
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struct clk_divider *divider;
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unsigned int div, value;
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unsigned long flags = 0;
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u32 val;
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if (!hw || !rate)
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@ -228,9 +227,6 @@ static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
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if (value > div_mask(divider))
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value = div_mask(divider);
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if (divider->lock)
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spin_lock_irqsave(divider->lock, flags);
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if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
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val = div_mask(divider) << (divider->shift + 16);
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} else {
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@ -240,9 +236,6 @@ static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
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val |= value << divider->shift;
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ti_clk_ll_ops->clk_writel(val, divider->reg);
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if (divider->lock)
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spin_unlock_irqrestore(divider->lock, flags);
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return 0;
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}
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@ -256,8 +249,7 @@ static struct clk *_register_divider(struct device *dev, const char *name,
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const char *parent_name,
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unsigned long flags, void __iomem *reg,
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u8 shift, u8 width, u8 clk_divider_flags,
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const struct clk_div_table *table,
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spinlock_t *lock)
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const struct clk_div_table *table)
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{
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struct clk_divider *div;
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struct clk *clk;
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@ -288,7 +280,6 @@ static struct clk *_register_divider(struct device *dev, const char *name,
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div->shift = shift;
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div->width = width;
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div->flags = clk_divider_flags;
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div->lock = lock;
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div->hw.init = &init;
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div->table = table;
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@ -421,7 +412,7 @@ struct clk *ti_clk_register_divider(struct ti_clk *setup)
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clk = _register_divider(NULL, setup->name, div->parent,
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flags, (void __iomem *)reg, div->bit_shift,
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width, div_flags, table, NULL);
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width, div_flags, table);
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if (IS_ERR(clk))
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kfree(table);
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|
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@ -584,8 +575,7 @@ static void __init of_ti_divider_clk_setup(struct device_node *node)
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goto cleanup;
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clk = _register_divider(NULL, node->name, parent_name, flags, reg,
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shift, width, clk_divider_flags, table,
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NULL);
|
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shift, width, clk_divider_flags, table);
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|
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if (!IS_ERR(clk)) {
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of_clk_add_provider(node, of_clk_src_simple_get, clk);
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|
|
|
|||
|
|
@ -168,7 +168,7 @@ static unsigned long ti_fapll_recalc_rate(struct clk_hw *hw,
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{
|
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struct fapll_data *fd = to_fapll(hw);
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u32 fapll_n, fapll_p, v;
|
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long long rate;
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u64 rate;
|
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|
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if (ti_fapll_clock_is_bypass(fd))
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return parent_rate;
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|
|
@ -314,7 +314,7 @@ static unsigned long ti_fapll_synth_recalc_rate(struct clk_hw *hw,
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{
|
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struct fapll_synth *synth = to_synth(hw);
|
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u32 synth_div_m;
|
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long long rate;
|
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u64 rate;
|
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|
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/* The audio_pll_clk1 is hardwired to produce 32.768KiHz clock */
|
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if (!synth->div)
|
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|
|
|
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|
|
@ -69,7 +69,6 @@ static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clk_mux *mux = to_clk_mux(hw);
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u32 val;
|
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unsigned long flags = 0;
|
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|
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if (mux->table) {
|
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index = mux->table[index];
|
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|
|
@ -81,9 +80,6 @@ static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index)
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index++;
|
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}
|
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|
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if (mux->lock)
|
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spin_lock_irqsave(mux->lock, flags);
|
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|
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if (mux->flags & CLK_MUX_HIWORD_MASK) {
|
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val = mux->mask << (mux->shift + 16);
|
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} else {
|
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|
|
@ -93,9 +89,6 @@ static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index)
|
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val |= index << mux->shift;
|
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ti_clk_ll_ops->clk_writel(val, mux->reg);
|
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|
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if (mux->lock)
|
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spin_unlock_irqrestore(mux->lock, flags);
|
||||
|
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return 0;
|
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}
|
||||
|
||||
|
|
@ -109,7 +102,7 @@ static struct clk *_register_mux(struct device *dev, const char *name,
|
|||
const char **parent_names, u8 num_parents,
|
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unsigned long flags, void __iomem *reg,
|
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u8 shift, u32 mask, u8 clk_mux_flags,
|
||||
u32 *table, spinlock_t *lock)
|
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u32 *table)
|
||||
{
|
||||
struct clk_mux *mux;
|
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struct clk *clk;
|
||||
|
|
@ -133,7 +126,6 @@ static struct clk *_register_mux(struct device *dev, const char *name,
|
|||
mux->shift = shift;
|
||||
mux->mask = mask;
|
||||
mux->flags = clk_mux_flags;
|
||||
mux->lock = lock;
|
||||
mux->table = table;
|
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mux->hw.init = &init;
|
||||
|
||||
|
|
@ -175,7 +167,7 @@ struct clk *ti_clk_register_mux(struct ti_clk *setup)
|
|||
|
||||
return _register_mux(NULL, setup->name, mux->parents, mux->num_parents,
|
||||
flags, (void __iomem *)reg, mux->bit_shift, mask,
|
||||
mux_flags, NULL, NULL);
|
||||
mux_flags, NULL);
|
||||
}
|
||||
|
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/**
|
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@ -227,8 +219,7 @@ static void of_mux_clk_setup(struct device_node *node)
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mask = (1 << fls(mask)) - 1;
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clk = _register_mux(NULL, node->name, parent_names, num_parents,
|
||||
flags, reg, shift, mask, clk_mux_flags, NULL,
|
||||
NULL);
|
||||
flags, reg, shift, mask, clk_mux_flags, NULL);
|
||||
|
||||
if (!IS_ERR(clk))
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||||
of_clk_add_provider(node, of_clk_src_simple_get, clk);
|
||||
|
|
|
|||
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Reference in New Issue