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powerpc/ipic: Support edge on IRQ0 

External IRQ0 (index 48) has the same capabilities as the other IRQ1-7
and is handled by the same register IPIC_SEPNR. When this register is
not specified for "ack" in "ipic_info", you cannot configure this IRQ
as IRQ_TYPE_EDGE_FALLING. This oversight was probably due to the
non-contiguous hwirq numbering of IRQ0 in the IPIC.

Signed-off-by: Jurgen Schindele <schindele@nentec.de>
[scottwood: Cleaned up commit message and posted as a proper patch]
Signed-off-by: Scott Wood <oss@buserror.net>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Scott Wood 2017-06-24 21:39:05 -05:00 committed by Michael Ellerman
parent 8f36479d0e
commit 446183e406
1 changed files with 1 additions and 0 deletions
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arch/powerpc/sysdev/ipic.c
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@ -315,6 +315,7 @@ static struct ipic_info ipic_info[] = {
.prio_mask = 7, .prio_mask = 7,
}, },
[48] = { [48] = {
.ack = IPIC_SEPNR,
.mask = IPIC_SEMSR, .mask = IPIC_SEMSR,
.prio = IPIC_SMPRR_A, .prio = IPIC_SMPRR_A,
.force = IPIC_SEFCR, .force = IPIC_SEFCR,