drm/amdgpu:impl vgt_flush for VI(V5)
when shadowing enabled, tesselation app will trigger vm fault because below three tesselation registers: VGT_TF_RING_SIZE__CI__VI, VGT_HS_OFFCHIP_PARAM__CI__VI, VGT_TF_MEMORY_BASE__CI__VI, need to be programed after vgt-flush. Tesselation picture vm fault disappeared after vgt-flush introduced. v2:implement vgt-flush for CI & SI. v3:move vgt flush inside of cntx_cntrl v4:count vgt flush in frame_size v5:squash in typo fix Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Monk Liu
Alex Deucher
parent
79abf1add6
commit
45682886bc
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@ -426,7 +426,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
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break;
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case 1:
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case 1:
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gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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@ -446,7 +446,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
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break;
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case 3:
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case 3:
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gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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@ -456,7 +456,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
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break;
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case 4:
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case 4:
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gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
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MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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@ -466,7 +466,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
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break;
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case 5:
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case 5:
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gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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@ -476,7 +476,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
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break;
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case 6:
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case 6:
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gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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@ -486,7 +486,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
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break;
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case 7:
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case 7:
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gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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@ -496,7 +496,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
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break;
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case 8:
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case 8:
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gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
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MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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@ -506,7 +506,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
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break;
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case 9:
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case 9:
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gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
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MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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@ -516,7 +516,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
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break;
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case 10:
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case 10:
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gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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@ -526,7 +526,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
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break;
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case 11:
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case 11:
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gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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@ -536,7 +536,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
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break;
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case 12:
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case 12:
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gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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@ -546,7 +546,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
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break;
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case 13:
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case 13:
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gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
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MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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@ -556,7 +556,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
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break;
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case 14:
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case 14:
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gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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@ -566,7 +566,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
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break;
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case 15:
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case 15:
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gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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@ -576,7 +576,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
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break;
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case 16:
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case 16:
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gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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@ -586,7 +586,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
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break;
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case 17:
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case 17:
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gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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@ -596,7 +596,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
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break;
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case 21:
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case 21:
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gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
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PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
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@ -606,7 +606,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
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break;
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case 22:
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case 22:
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gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
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PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
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@ -616,7 +616,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
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break;
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case 23:
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case 23:
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gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
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PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
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@ -626,7 +626,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
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break;
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case 24:
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case 24:
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gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
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PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
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@ -636,7 +636,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
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break;
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case 25:
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case 25:
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gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
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PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
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@ -1463,6 +1463,13 @@ static void gfx_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
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amdgpu_ring_write(ring, 0x1);
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}
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static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
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{
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amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
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amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
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EVENT_INDEX(0));
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}
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/**
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* gfx_v6_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp
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*
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@ -1917,7 +1924,7 @@ static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev)
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static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
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bool enable)
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{
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{
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u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
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u32 mask;
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int i;
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@ -2802,6 +2809,8 @@ static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev)
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static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
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{
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if (flags & AMDGPU_HAVE_CTX_SWITCH)
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gfx_v6_0_ring_emit_vgt_flush(ring);
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amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
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amdgpu_ring_write(ring, 0x80000000);
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amdgpu_ring_write(ring, 0);
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@ -3265,7 +3274,7 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
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14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
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7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */
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17 + 6 + /* gfx_v6_0_ring_emit_vm_flush */
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3, /* gfx_v6_ring_emit_cntxcntl */
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3 + 2, /* gfx_v6_ring_emit_cntxcntl including vgt flush */
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.emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */
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.emit_ib = gfx_v6_0_ring_emit_ib,
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.emit_fence = gfx_v6_0_ring_emit_fence,
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@ -2105,6 +2105,18 @@ static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
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amdgpu_ring_write(ring, 0x20); /* poll interval */
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}
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static void gfx_v7_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
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{
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amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
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amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) |
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EVENT_INDEX(4));
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amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
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amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
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EVENT_INDEX(0));
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}
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/**
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* gfx_v7_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp
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*
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@ -2260,6 +2272,7 @@ static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
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dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
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if (flags & AMDGPU_HAVE_CTX_SWITCH) {
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gfx_v7_0_ring_emit_vgt_flush(ring);
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/* set load_global_config & load_global_uconfig */
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dw2 |= 0x8001;
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/* set load_cs_sh_regs */
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@ -5153,7 +5166,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
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12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user fence, vm fence */
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7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */
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17 + 6 + /* gfx_v7_0_ring_emit_vm_flush */
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3, /* gfx_v7_ring_emit_cntxcntl */
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3 + 4, /* gfx_v7_ring_emit_cntxcntl including vgt flush*/
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.emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_gfx */
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.emit_ib = gfx_v7_0_ring_emit_ib_gfx,
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.emit_fence = gfx_v7_0_ring_emit_fence_gfx,
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@ -6186,6 +6186,18 @@ static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
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amdgpu_ring_write(ring, 0x20); /* poll interval */
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}
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static void gfx_v8_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
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{
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amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
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amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) |
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EVENT_INDEX(4));
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amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
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amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
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EVENT_INDEX(0));
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}
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static void gfx_v8_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
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{
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amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
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@ -6371,6 +6383,7 @@ static void gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
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dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
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if (flags & AMDGPU_HAVE_CTX_SWITCH) {
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gfx_v8_0_ring_emit_vgt_flush(ring);
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/* set load_global_config & load_global_uconfig */
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dw2 |= 0x8001;
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/* set load_cs_sh_regs */
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@ -6574,7 +6587,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
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7 + /* gfx_v8_0_ring_emit_pipeline_sync */
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128 + 19 + /* gfx_v8_0_ring_emit_vm_flush */
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||||
2 + /* gfx_v8_ring_emit_sb */
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3, /* gfx_v8_ring_emit_cntxcntl */
|
||||
3 + 4, /* gfx_v8_ring_emit_cntxcntl including vgt flush */
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.emit_ib_size = 4, /* gfx_v8_0_ring_emit_ib_gfx */
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.emit_ib = gfx_v8_0_ring_emit_ib_gfx,
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||||
.emit_fence = gfx_v8_0_ring_emit_fence_gfx,
|
||||
|
|
|
|||
Loading…
Reference in New Issue