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ARM: asm: Add ARM_BE8() assembly helper 

Add ARM_BE8() helper to wrap any code conditional on being
compile when CONFIG_ARM_ENDIAN_BE8 is selected and convert
existing places where this is to use it.

Acked-by: Nicolas Pitre <nico@linaro.org>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
This commit is contained in:
Ben Dooks 2013-02-12 18:59:57 +00:00
parent d10d2d4854
commit 457c2403c5
7 changed files with 16 additions and 21 deletions

8
arch/arm/boot/compressed/head.S
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@ -699,9 +699,7 @@ __armv4_mmu_cache_on:
mrc p15, 0, r0, c1, c0, 0 @ read control reg mrc p15, 0, r0, c1, c0, 0 @ read control reg
orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
orr r0, r0, #0x0030 orr r0, r0, #0x0030
#ifdef CONFIG_CPU_ENDIAN_BE8 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
orr r0, r0, #1 << 25 @ big-endian page tables
#endif
bl __common_mmu_cache_on bl __common_mmu_cache_on
mov r0, #0 mov r0, #0
mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
@ -728,9 +726,7 @@ __armv7_mmu_cache_on:
orr r0, r0, #1 << 22 @ U (v6 unaligned access model) orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
@ (needed for ARM1176) @ (needed for ARM1176)
#ifdef CONFIG_MMU #ifdef CONFIG_MMU
#ifdef CONFIG_CPU_ENDIAN_BE8 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
orr r0, r0, #1 << 25 @ big-endian page tables
#endif
mrcne p15, 0, r6, c2, c0, 2 @ read ttb control reg mrcne p15, 0, r6, c2, c0, 2 @ read ttb control reg
orrne r0, r0, #1 @ MMU enabled orrne r0, r0, #1 @ MMU enabled
movne r1, #0xfffffffd @ domain 0 = client movne r1, #0xfffffffd @ domain 0 = client

7
arch/arm/include/asm/assembler.h
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@ -53,6 +53,13 @@
#define put_byte_3 lsl #0 #define put_byte_3 lsl #0
#endif #endif
/* Select code for any configuration running in BE8 mode */
#ifdef CONFIG_CPU_ENDIAN_BE8
#define ARM_BE8(code...) code
#else
#define ARM_BE8(code...)
#endif
/* /*
* Data preload for architectures that support it * Data preload for architectures that support it
*/ */

5
arch/arm/kernel/entry-armv.S
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@ -416,9 +416,8 @@ __und_usr:
bne __und_usr_thumb bne __und_usr_thumb
sub r4, r2, #4 @ ARM instr at LR - 4 sub r4, r2, #4 @ ARM instr at LR - 4
1: ldrt r0, [r4] 1: ldrt r0, [r4]
#ifdef CONFIG_CPU_ENDIAN_BE8 ARM_BE8(rev r0, r0) @ little endian instruction
rev r0, r0 @ little endian instruction
#endif
@ r0 = 32-bit ARM instruction which caused the exception @ r0 = 32-bit ARM instruction which caused the exception
@ r2 = PC value for the following instruction (:= regs->ARM_pc) @ r2 = PC value for the following instruction (:= regs->ARM_pc)
@ r4 = PC value for the faulting instruction @ r4 = PC value for the faulting instruction

4
arch/arm/kernel/entry-common.S
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@ -393,9 +393,7 @@ ENTRY(vector_swi)
#else #else
USER( ldr r10, [lr, #-4] ) @ get SWI instruction USER( ldr r10, [lr, #-4] ) @ get SWI instruction
#endif #endif
#ifdef CONFIG_CPU_ENDIAN_BE8 ARM_BE8(rev r10, r10) @ little endian instruction
rev r10, r10 @ little endian instruction
#endif
#elif defined(CONFIG_AEABI) #elif defined(CONFIG_AEABI)

5
arch/arm/mm/abort-ev6.S
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@ -38,9 +38,8 @@ ENTRY(v6_early_abort)
bne do_DataAbort bne do_DataAbort
bic r1, r1, #1 << 11 @ clear bit 11 of FSR bic r1, r1, #1 << 11 @ clear bit 11 of FSR
ldr r3, [r4] @ read aborted ARM instruction ldr r3, [r4] @ read aborted ARM instruction
#ifdef CONFIG_CPU_ENDIAN_BE8 ARM_BE8(rev r3, r3)
rev r3, r3
#endif
do_ldrd_abort tmp=ip, insn=r3 do_ldrd_abort tmp=ip, insn=r3
tst r3, #1 << 20 @ L = 0 -> write tst r3, #1 << 20 @ L = 0 -> write
orreq r1, r1, #1 << 11 @ yes. orreq r1, r1, #1 << 11 @ yes.

4
arch/arm/mm/proc-v6.S
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@ -220,9 +220,7 @@ __v6_setup:
#endif /* CONFIG_MMU */ #endif /* CONFIG_MMU */
adr r5, v6_crval adr r5, v6_crval
ldmia r5, {r5, r6} ldmia r5, {r5, r6}
#ifdef CONFIG_CPU_ENDIAN_BE8 ARM_BE8(orr r6, r6, #1 << 25) @ big-endian page tables
orr r6, r6, #1 << 25 @ big-endian page tables
#endif
mrc p15, 0, r0, c1, c0, 0 @ read control register mrc p15, 0, r0, c1, c0, 0 @ read control register
bic r0, r0, r5 @ clear bits them bic r0, r0, r5 @ clear bits them
orr r0, r0, r6 @ set them orr r0, r0, r6 @ set them

4
arch/arm/mm/proc-v7.S
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@ -367,9 +367,7 @@ __v7_setup:
#endif #endif
adr r5, v7_crval adr r5, v7_crval
ldmia r5, {r5, r6} ldmia r5, {r5, r6}
#ifdef CONFIG_CPU_ENDIAN_BE8 ARM_BE8(orr r6, r6, #1 << 25) @ big-endian page tables
orr r6, r6, #1 << 25 @ big-endian page tables
#endif
#ifdef CONFIG_SWP_EMULATE #ifdef CONFIG_SWP_EMULATE
orr r5, r5, #(1 << 10) @ set SW bit in "clear" orr r5, r5, #(1 << 10) @ set SW bit in "clear"
bic r6, r6, #(1 << 10) @ clear it in "mmuset" bic r6, r6, #(1 << 10) @ clear it in "mmuset"