riscv: dts: Re-organize the DT nodes
As per the convention for any SOC device with external connection, define only device DT node in SOC DTSi file with status = "disabled" and enable device in Board DTS file with status = "okay" Reported-by: Anup Patel <anup@brainfault.org> Signed-off-by: Yash Shah <yash.shah@sifive.com> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
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@ -163,6 +163,7 @@ uart0: serial@10010000 {
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interrupt-parent = <&plic0>;
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interrupts = <4>;
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clocks = <&prci PRCI_CLK_TLCLK>;
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status = "disabled";
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};
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uart1: serial@10011000 {
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compatible = "sifive,fu540-c000-uart", "sifive,uart0";
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@ -170,6 +171,7 @@ uart1: serial@10011000 {
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interrupt-parent = <&plic0>;
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interrupts = <5>;
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clocks = <&prci PRCI_CLK_TLCLK>;
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status = "disabled";
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};
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i2c0: i2c@10030000 {
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compatible = "sifive,fu540-c000-i2c", "sifive,i2c0";
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@ -181,6 +183,7 @@ i2c0: i2c@10030000 {
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reg-io-width = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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qspi0: spi@10040000 {
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compatible = "sifive,fu540-c000-spi", "sifive,spi0";
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@ -191,6 +194,7 @@ qspi0: spi@10040000 {
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clocks = <&prci PRCI_CLK_TLCLK>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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qspi1: spi@10041000 {
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compatible = "sifive,fu540-c000-spi", "sifive,spi0";
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@ -201,6 +205,7 @@ qspi1: spi@10041000 {
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clocks = <&prci PRCI_CLK_TLCLK>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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qspi2: spi@10050000 {
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compatible = "sifive,fu540-c000-spi", "sifive,spi0";
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@ -210,6 +215,7 @@ qspi2: spi@10050000 {
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clocks = <&prci PRCI_CLK_TLCLK>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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};
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@ -42,7 +42,20 @@ rtcclk: rtcclk {
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};
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};
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&uart0 {
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status = "okay";
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};
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&uart1 {
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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};
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&qspi0 {
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status = "okay";
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flash@0 {
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compatible = "issi,is25wp256", "jedec,spi-nor";
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reg = <0>;
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