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clk: hi3798cv200: correct IR clock parent 

The IR clock is sourced from '24m' rather than '100m'.  Correct it.

Signed-off-by: Younian Wang <wangyounian@hisilicon.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This commit is contained in:
Younian Wang 2018-01-24 19:48:24 +08:00 committed by Shawn Guo
parent 055d56891e
commit 47629f6765
1 changed files with 1 additions and 1 deletions
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drivers/clk/hisilicon/crg-hi3798cv200.c
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@ -244,7 +244,7 @@ static const struct hisi_crg_funcs hi3798cv200_crg_funcs = {
#define HI3798CV200_SYSCTRL_NR_CLKS 16 #define HI3798CV200_SYSCTRL_NR_CLKS 16
static const struct hisi_gate_clock hi3798cv200_sysctrl_gate_clks[] = { static const struct hisi_gate_clock hi3798cv200_sysctrl_gate_clks[] = {
{ HISTB_IR_CLK, "clk_ir", "100m", { HISTB_IR_CLK, "clk_ir", "24m",
CLK_SET_RATE_PARENT, 0x48, 4, 0, }, CLK_SET_RATE_PARENT, 0x48, 4, 0, },
{ HISTB_TIMER01_CLK, "clk_timer01", "24m", { HISTB_TIMER01_CLK, "clk_timer01", "24m",
CLK_SET_RATE_PARENT, 0x48, 6, 0, }, CLK_SET_RATE_PARENT, 0x48, 6, 0, },