just some lonely amd fixes

-----BEGIN PGP SIGNATURE-----
 
 iQIcBAABAgAGBQJZhBe5AAoJEAx081l5xIa+NR8P/02fl5JHVXaPpSvR+VmFzaCD
 05yYdc56QhWv81lUWAHEP+pFJTMv49y8qyekqDdEDI4CCP8uU+Sc4zPQ/BgW/62c
 9Yqy7RwigEp8FqqttEb3s6RW2OnLTfgXnwvLzXRDyMUkUUBOtL545lgOG/Vrz3Id
 c+uRrNXlxYuSfoSjoiqP6VsBXXEYI0eZS9oWWlnTsGAvCI3JK/pSTfj9m9nfdXZ/
 ByghEEB+PE59m2nP/egp5CJd/3fJ5GVXqK7ROObpz1Hkd7dSZjVALtLE+KB3bUuV
 OvCfStGwfEHs3lMmjxahIn4fBWOeBh0OtQd3j36It7i0aeTPVpXH+o/O1EseT7Ka
 gQjr7miBGlZPSJ+EkqObG3Dv2EL3/2S8dDVOLaXbtHXsZHIebumDJ3ogDNq0xPpU
 mZjtNBvlDbwzmm7dSw6r9rHZBUzCfCEefmYkVS4tVBl2vMoXQJA6FrYGtgVV2eZO
 xUNEgTcmLqMcP38q9/UWC0ZBOQJLoEY5SfVVaLzIIKqHSBJjAbVJXmrrIuVSmnFT
 Kie0eBOtMcsToJh7yUR+vvTAByZg4bl8j3hZlX0PtyRwxpavzMvBiHYa4gE2CpU3
 EwU7JjqF346CdMvgiRZHpBZXKnGKSrVSDtdnlFrR5C5H7XWTJO3rRPKexcyrCc1F
 bNo/diEu4KmywYrXA1tT
 =nQKg
 -----END PGP SIGNATURE-----

Merge tag 'drm-fixes-for-v4.13-rc4' of git://people.freedesktop.org/~airlied/linux

Pull drm fixes from Dave Airlie:
 "Either my email ate everything or everyone is on holidays, either way
  all I can find is some lonely AMD fixes"

[ Europe might be on vacation, and the Pacific NW is too hot for work. ]

* tag 'drm-fixes-for-v4.13-rc4' of git://people.freedesktop.org/~airlied/linux:
  drm/amdgpu: Use list_del_init in amdgpu_mn_unregister
  drm/amdgpu: Fix undue fallthroughs in golden registers initialization
  drm/amdgpu: fix header on gfx9 clear state
This commit is contained in:
Linus Torvalds 2017-08-04 09:59:24 -07:00
commit 47d47585d0
3 changed files with 24 additions and 21 deletions

View File

@ -359,7 +359,7 @@ void amdgpu_mn_unregister(struct amdgpu_bo *bo)
head = bo->mn_list.next;
bo->mn = NULL;
list_del(&bo->mn_list);
list_del_init(&bo->mn_list);
if (list_empty(head)) {
struct amdgpu_mn_node *node;

View File

@ -1,24 +1,25 @@
/*
***************************************************************************************************
*
* Trade secret of Advanced Micro Devices, Inc.
* Copyright (c) 2010 Advanced Micro Devices, Inc. (unpublished)
*
* All rights reserved. This notice is intended as a precaution against inadvertent publication and
* does not imply publication or any waiver of confidentiality. The year included in the foregoing
* notice is the year of creation of the work.
*
***************************************************************************************************
*/
/**
***************************************************************************************************
* @brief gfx9 Clearstate Definitions
***************************************************************************************************
*
* Do not edit! This is a machine-generated file!
*
*/
* Copyright 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
static const unsigned int gfx9_SECT_CONTEXT_def_1[] =
{

View File

@ -1385,6 +1385,7 @@ static void si_init_golden_registers(struct amdgpu_device *adev)
amdgpu_program_register_sequence(adev,
pitcairn_mgcg_cgcg_init,
(const u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
break;
case CHIP_VERDE:
amdgpu_program_register_sequence(adev,
verde_golden_registers,
@ -1409,6 +1410,7 @@ static void si_init_golden_registers(struct amdgpu_device *adev)
amdgpu_program_register_sequence(adev,
oland_mgcg_cgcg_init,
(const u32)ARRAY_SIZE(oland_mgcg_cgcg_init));
break;
case CHIP_HAINAN:
amdgpu_program_register_sequence(adev,
hainan_golden_registers,