just some lonely amd fixes
-----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJZhBe5AAoJEAx081l5xIa+NR8P/02fl5JHVXaPpSvR+VmFzaCD 05yYdc56QhWv81lUWAHEP+pFJTMv49y8qyekqDdEDI4CCP8uU+Sc4zPQ/BgW/62c 9Yqy7RwigEp8FqqttEb3s6RW2OnLTfgXnwvLzXRDyMUkUUBOtL545lgOG/Vrz3Id c+uRrNXlxYuSfoSjoiqP6VsBXXEYI0eZS9oWWlnTsGAvCI3JK/pSTfj9m9nfdXZ/ ByghEEB+PE59m2nP/egp5CJd/3fJ5GVXqK7ROObpz1Hkd7dSZjVALtLE+KB3bUuV OvCfStGwfEHs3lMmjxahIn4fBWOeBh0OtQd3j36It7i0aeTPVpXH+o/O1EseT7Ka gQjr7miBGlZPSJ+EkqObG3Dv2EL3/2S8dDVOLaXbtHXsZHIebumDJ3ogDNq0xPpU mZjtNBvlDbwzmm7dSw6r9rHZBUzCfCEefmYkVS4tVBl2vMoXQJA6FrYGtgVV2eZO xUNEgTcmLqMcP38q9/UWC0ZBOQJLoEY5SfVVaLzIIKqHSBJjAbVJXmrrIuVSmnFT Kie0eBOtMcsToJh7yUR+vvTAByZg4bl8j3hZlX0PtyRwxpavzMvBiHYa4gE2CpU3 EwU7JjqF346CdMvgiRZHpBZXKnGKSrVSDtdnlFrR5C5H7XWTJO3rRPKexcyrCc1F bNo/diEu4KmywYrXA1tT =nQKg -----END PGP SIGNATURE----- Merge tag 'drm-fixes-for-v4.13-rc4' of git://people.freedesktop.org/~airlied/linux Pull drm fixes from Dave Airlie: "Either my email ate everything or everyone is on holidays, either way all I can find is some lonely AMD fixes" [ Europe might be on vacation, and the Pacific NW is too hot for work. ] * tag 'drm-fixes-for-v4.13-rc4' of git://people.freedesktop.org/~airlied/linux: drm/amdgpu: Use list_del_init in amdgpu_mn_unregister drm/amdgpu: Fix undue fallthroughs in golden registers initialization drm/amdgpu: fix header on gfx9 clear state
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47d47585d0
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@ -359,7 +359,7 @@ void amdgpu_mn_unregister(struct amdgpu_bo *bo)
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head = bo->mn_list.next;
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bo->mn = NULL;
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list_del(&bo->mn_list);
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list_del_init(&bo->mn_list);
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if (list_empty(head)) {
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struct amdgpu_mn_node *node;
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@ -1,24 +1,25 @@
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/*
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***************************************************************************************************
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*
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* Trade secret of Advanced Micro Devices, Inc.
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* Copyright (c) 2010 Advanced Micro Devices, Inc. (unpublished)
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*
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* All rights reserved. This notice is intended as a precaution against inadvertent publication and
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* does not imply publication or any waiver of confidentiality. The year included in the foregoing
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* notice is the year of creation of the work.
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*
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***************************************************************************************************
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*/
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/**
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***************************************************************************************************
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* @brief gfx9 Clearstate Definitions
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***************************************************************************************************
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*
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* Do not edit! This is a machine-generated file!
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*
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*/
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* Copyright 2017 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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static const unsigned int gfx9_SECT_CONTEXT_def_1[] =
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{
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@ -1385,6 +1385,7 @@ static void si_init_golden_registers(struct amdgpu_device *adev)
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amdgpu_program_register_sequence(adev,
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pitcairn_mgcg_cgcg_init,
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(const u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
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break;
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case CHIP_VERDE:
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amdgpu_program_register_sequence(adev,
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verde_golden_registers,
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@ -1409,6 +1410,7 @@ static void si_init_golden_registers(struct amdgpu_device *adev)
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amdgpu_program_register_sequence(adev,
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oland_mgcg_cgcg_init,
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(const u32)ARRAY_SIZE(oland_mgcg_cgcg_init));
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break;
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case CHIP_HAINAN:
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amdgpu_program_register_sequence(adev,
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hainan_golden_registers,
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