drm/amd/pp: Fix pp_sclk/mclk_od not work on Vega10
not update dpm table with user's setting. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -3249,6 +3249,37 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
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static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
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static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
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{
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{
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struct vega10_hwmgr *data = hwmgr->backend;
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struct vega10_hwmgr *data = hwmgr->backend;
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const struct phm_set_power_state_input *states =
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(const struct phm_set_power_state_input *)input;
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const struct vega10_power_state *vega10_ps =
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cast_const_phw_vega10_power_state(states->pnew_state);
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struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
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uint32_t sclk = vega10_ps->performance_levels
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[vega10_ps->performance_level_count - 1].gfx_clock;
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struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
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uint32_t mclk = vega10_ps->performance_levels
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[vega10_ps->performance_level_count - 1].mem_clock;
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uint32_t i;
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for (i = 0; i < sclk_table->count; i++) {
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if (sclk == sclk_table->dpm_levels[i].value)
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break;
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}
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if (i >= sclk_table->count) {
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data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
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sclk_table->dpm_levels[i-1].value = sclk;
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}
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for (i = 0; i < mclk_table->count; i++) {
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if (mclk == mclk_table->dpm_levels[i].value)
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break;
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}
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if (i >= mclk_table->count) {
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data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
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mclk_table->dpm_levels[i-1].value = mclk;
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}
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if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
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if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
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data->need_update_dpm_table |= DPMTABLE_UPDATE_MCLK;
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data->need_update_dpm_table |= DPMTABLE_UPDATE_MCLK;
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