b43: N-PHY: update generic rev7+ workarounds
Add some missing ops and prepare for new devices support. This patch is a great stability improvement for BCM43217. Earlier Tenda W322E used to disconnect every 2 minutes (16 times over 30 minutes). With this fix I got it running for 4 hours (with iperf) without any disconnection. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Rafał Miłecki
John W. Linville
parent
6b346e54bf
commit
49083b47a3
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@ -2708,15 +2708,19 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
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struct ssb_sprom *sprom = dev->dev->bus_sprom;
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struct b43_phy *phy = &dev->phy;
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/* TX to RX */
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u8 tx2rx_events[7] = { 4, 3, 5, 2, 1, 8, 31, };
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u8 tx2rx_delays[7] = { 8, 4, 4, 4, 4, 6, 1, };
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/* RX to TX */
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u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
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0x1F };
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u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
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u16 ntab7_15e_16e[] = { 0x10f, 0x10f };
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static const u16 ntab7_15e_16e[] = { 0, 0x10f, 0x10f };
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u8 ntab7_138_146[] = { 0x11, 0x11 };
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u8 ntab7_133[] = { 0x77, 0x11, 0x11 };
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u16 lpf_20, lpf_40, lpf_11b;
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u16 lpf_ofdm_20mhz, lpf_ofdm_40mhz, lpf_11b;
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u16 bcap_val, bcap_val_11b, bcap_val_11n_20, bcap_val_11n_40;
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u16 scap_val, scap_val_11b, scap_val_11n_20, scap_val_11n_40;
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bool rccal_ovrd = false;
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@ -2727,6 +2731,13 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
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u32 tmp32;
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u8 core;
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b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
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b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01b3);
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b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
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b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016e);
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b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00cd);
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b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
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if (phy->rev == 7) {
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b43_phy_set(dev, B43_NPHY_FINERX2_CGC, 0x10);
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b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0xFF80, 0x0020);
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@ -2746,11 +2757,18 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
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b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0xFF80, 0x0040);
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b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0x80FF, 0x4000);
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}
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if (phy->rev <= 8) {
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if (phy->rev >= 16) {
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b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x7ff);
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b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x7ff);
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} else if (phy->rev <= 8) {
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b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1B0);
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b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1B0);
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}
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if (phy->rev >= 8)
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if (phy->rev >= 16)
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b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0xa0);
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else if (phy->rev >= 8)
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b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0x72);
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b43_ntab_write(dev, B43_NTAB16(8, 0x00), 2);
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@ -2758,9 +2776,11 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
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tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
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tmp32 &= 0xffffff;
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b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
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b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x15e), 2, ntab7_15e_16e);
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b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x16e), 2, ntab7_15e_16e);
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b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x15d), 3, ntab7_15e_16e);
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b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x16d), 3, ntab7_15e_16e);
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b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays,
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ARRAY_SIZE(tx2rx_events));
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if (b43_nphy_ipa(dev))
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b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
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rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
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@ -2768,44 +2788,53 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
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b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_0, 0x3FFF, 0x4000);
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b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_1, 0x3FFF, 0x4000);
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lpf_20 = b43_nphy_read_lpf_ctl(dev, 0x154);
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lpf_40 = b43_nphy_read_lpf_ctl(dev, 0x159);
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lpf_ofdm_20mhz = b43_nphy_read_lpf_ctl(dev, 0x154);
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lpf_ofdm_40mhz = b43_nphy_read_lpf_ctl(dev, 0x159);
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lpf_11b = b43_nphy_read_lpf_ctl(dev, 0x152);
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bcap_val = b43_radio_read(dev, R2057_RCCAL_BCAP_VAL);
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scap_val = b43_radio_read(dev, R2057_RCCAL_SCAP_VAL);
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if (b43_nphy_ipa(dev)) {
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if ((phy->radio_rev == 5 && b43_is_40mhz(dev)) ||
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phy->radio_rev == 7 || phy->radio_rev == 8) {
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bcap_val = b43_radio_read(dev, 0x16b);
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scap_val = b43_radio_read(dev, 0x16a);
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scap_val_11b = scap_val;
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bcap_val_11b = bcap_val;
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if (phy->radio_rev == 5 && b43_is_40mhz(dev)) {
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switch (phy->radio_rev) {
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case 5:
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/* Check radio version (to be 0) by PHY rev for now */
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if (phy->rev == 8 && b43_is_40mhz(dev)) {
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scap_val_11b = scap_val;
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bcap_val_11b = bcap_val;
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scap_val_11n_20 = scap_val;
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bcap_val_11n_20 = bcap_val;
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scap_val_11n_40 = bcap_val_11n_40 = 0xc;
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rccal_ovrd = true;
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} else { /* Rev 7/8 */
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lpf_20 = 4;
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lpf_11b = 1;
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if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
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scap_val_11n_20 = 0xc;
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bcap_val_11n_20 = 0xc;
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scap_val_11n_40 = 0xa;
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bcap_val_11n_40 = 0xa;
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} else {
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scap_val_11n_20 = 0x14;
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bcap_val_11n_20 = 0x14;
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scap_val_11n_40 = 0xf;
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bcap_val_11n_40 = 0xf;
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}
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rccal_ovrd = true;
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}
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if (phy->rev == 9) {
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/* TODO: Radio version 1 (e.g. BCM5357B0) */
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}
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break;
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case 7:
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case 8:
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scap_val_11b = scap_val;
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bcap_val_11b = bcap_val;
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lpf_ofdm_20mhz = 4;
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lpf_11b = 1;
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if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
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scap_val_11n_20 = 0xc;
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bcap_val_11n_20 = 0xc;
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scap_val_11n_40 = 0xa;
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bcap_val_11n_40 = 0xa;
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} else {
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scap_val_11n_20 = 0x14;
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bcap_val_11n_20 = 0x14;
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scap_val_11n_40 = 0xf;
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bcap_val_11n_40 = 0xf;
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}
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rccal_ovrd = true;
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break;
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}
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} else {
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if (phy->radio_rev == 5) {
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lpf_20 = 1;
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lpf_40 = 3;
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bcap_val = b43_radio_read(dev, 0x16b);
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scap_val = b43_radio_read(dev, 0x16a);
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lpf_ofdm_20mhz = 1;
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lpf_ofdm_40mhz = 3;
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scap_val_11b = scap_val;
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bcap_val_11b = bcap_val;
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scap_val_11n_20 = 0x11;
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@ -2816,15 +2845,20 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
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}
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}
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if (rccal_ovrd) {
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rx2tx_lut_20_11b = (bcap_val_11b << 8) |
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u8 rx2tx_lut_extra = 1;
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rx2tx_lut_20_11b = (rx2tx_lut_extra << 13) |
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(bcap_val_11b << 8) |
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(scap_val_11b << 3) |
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lpf_11b;
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rx2tx_lut_20_11n = (bcap_val_11n_20 << 8) |
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rx2tx_lut_20_11n = (rx2tx_lut_extra << 13) |
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(bcap_val_11n_20 << 8) |
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(scap_val_11n_20 << 3) |
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lpf_20;
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rx2tx_lut_40_11n = (bcap_val_11n_40 << 8) |
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lpf_ofdm_20mhz;
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rx2tx_lut_40_11n = (rx2tx_lut_extra << 13) |
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(bcap_val_11n_40 << 8) |
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(scap_val_11n_40 << 3) |
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lpf_40;
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lpf_ofdm_40mhz;
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for (core = 0; core < 2; core++) {
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b43_ntab_write(dev, B43_NTAB16(7, 0x152 + core * 16),
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rx2tx_lut_20_11b);
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@ -2893,7 +2927,8 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
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0x7f);
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}
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}
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if (phy->radio_rev == 3) {
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switch (phy->radio_rev) {
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case 3:
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for (core = 0; core < 2; core++) {
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if (core == 0) {
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b43_radio_write(dev, 0x64,
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@ -2919,7 +2954,9 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
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0x3E);
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}
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}
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} else if (phy->radio_rev == 7 || phy->radio_rev == 8) {
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break;
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case 7:
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case 8:
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if (!b43_is_40mhz(dev)) {
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b43_radio_write(dev, 0x5F, 0x14);
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b43_radio_write(dev, 0xE8, 0x12);
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@ -2927,6 +2964,7 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
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b43_radio_write(dev, 0x5F, 0x16);
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b43_radio_write(dev, 0xE8, 0x16);
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}
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break;
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}
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} else {
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u16 freq = phy->chandef->chan->center_freq;
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