mtd: spi-nor: intel-spi: add support for Intel Cannon Lake SPI flash
Now that SPI flash controllers without a software sequencer are supported, it's trivial to add support for CNL and its PCI ID. Values from https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/300-series-chipset-pch-datasheet-vol-2.pdf Signed-off-by: Jethro Beekman <jethro@fortanix.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
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@ -20,6 +20,10 @@ static const struct intel_spi_boardinfo bxt_info = {
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.type = INTEL_SPI_BXT,
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};
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static const struct intel_spi_boardinfo cnl_info = {
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.type = INTEL_SPI_CNL,
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};
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static int intel_spi_pci_probe(struct pci_dev *pdev,
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const struct pci_device_id *id)
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{
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@ -68,6 +72,7 @@ static const struct pci_device_id intel_spi_pci_ids[] = {
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{ PCI_VDEVICE(INTEL, 0xa0a4), (unsigned long)&bxt_info },
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{ PCI_VDEVICE(INTEL, 0xa1a4), (unsigned long)&bxt_info },
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{ PCI_VDEVICE(INTEL, 0xa224), (unsigned long)&bxt_info },
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{ PCI_VDEVICE(INTEL, 0xa324), (unsigned long)&cnl_info },
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{ },
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};
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MODULE_DEVICE_TABLE(pci, intel_spi_pci_ids);
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@ -108,6 +108,10 @@
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#define BXT_FREG_NUM 12
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#define BXT_PR_NUM 6
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#define CNL_PR 0x84
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#define CNL_FREG_NUM 6
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#define CNL_PR_NUM 5
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#define LVSCC 0xc4
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#define UVSCC 0xc8
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#define ERASE_OPCODE_SHIFT 8
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@ -344,6 +348,13 @@ static int intel_spi_init(struct intel_spi *ispi)
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ispi->erase_64k = true;
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break;
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case INTEL_SPI_CNL:
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ispi->sregs = NULL;
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ispi->pregs = ispi->base + CNL_PR;
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ispi->nregions = CNL_FREG_NUM;
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ispi->pr_num = CNL_PR_NUM;
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break;
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default:
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return -EINVAL;
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}
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@ -13,6 +13,7 @@ enum intel_spi_type {
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INTEL_SPI_BYT = 1,
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INTEL_SPI_LPT,
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INTEL_SPI_BXT,
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INTEL_SPI_CNL,
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};
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/**
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