Revert "drm/radeon: adding synchronization for GRBM GFX"
This reverts commit 1c0a46255f. Not needed
anymore, since amdkfd is no longer supported with radeon.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Michel Dänzer <michel@daenzer.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Michel Dänzer
Alex Deucher
parent
923a50a686
commit
4c0ab318a1
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@ -1627,8 +1627,6 @@ static const u32 godavari_golden_registers[] =
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static void cik_init_golden_registers(struct radeon_device *rdev)
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{
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/* Some of the registers might be dependent on GRBM_GFX_INDEX */
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mutex_lock(&rdev->grbm_idx_mutex);
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switch (rdev->family) {
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case CHIP_BONAIRE:
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radeon_program_register_sequence(rdev,
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@ -1703,7 +1701,6 @@ static void cik_init_golden_registers(struct radeon_device *rdev)
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default:
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break;
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}
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mutex_unlock(&rdev->grbm_idx_mutex);
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}
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/**
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@ -3120,7 +3117,6 @@ static void cik_setup_rb(struct radeon_device *rdev,
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u32 disabled_rbs = 0;
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u32 enabled_rbs = 0;
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mutex_lock(&rdev->grbm_idx_mutex);
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for (i = 0; i < se_num; i++) {
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for (j = 0; j < sh_per_se; j++) {
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cik_select_se_sh(rdev, i, j);
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@ -3132,7 +3128,6 @@ static void cik_setup_rb(struct radeon_device *rdev,
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}
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}
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cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
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mutex_unlock(&rdev->grbm_idx_mutex);
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mask = 1;
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for (i = 0; i < max_rb_num_per_se * se_num; i++) {
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@ -3143,7 +3138,6 @@ static void cik_setup_rb(struct radeon_device *rdev,
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rdev->config.cik.backend_enable_mask = enabled_rbs;
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mutex_lock(&rdev->grbm_idx_mutex);
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for (i = 0; i < se_num; i++) {
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cik_select_se_sh(rdev, i, 0xffffffff);
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data = 0;
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@ -3171,7 +3165,6 @@ static void cik_setup_rb(struct radeon_device *rdev,
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WREG32(PA_SC_RASTER_CONFIG, data);
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}
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cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
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mutex_unlock(&rdev->grbm_idx_mutex);
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}
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/**
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@ -3391,12 +3384,6 @@ static void cik_gpu_init(struct radeon_device *rdev)
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/* set HW defaults for 3D engine */
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WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
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mutex_lock(&rdev->grbm_idx_mutex);
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/*
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* making sure that the following register writes will be broadcasted
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* to all the shaders
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*/
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cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
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WREG32(SX_DEBUG_1, 0x20);
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WREG32(TA_CNTL_AUX, 0x00010000);
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@ -3452,7 +3439,6 @@ static void cik_gpu_init(struct radeon_device *rdev)
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WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
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WREG32(PA_SC_ENHANCE, ENABLE_PA_SC_OUT_OF_ORDER);
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mutex_unlock(&rdev->grbm_idx_mutex);
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udelay(50);
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}
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@ -5830,7 +5816,6 @@ static void cik_wait_for_rlc_serdes(struct radeon_device *rdev)
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u32 i, j, k;
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u32 mask;
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mutex_lock(&rdev->grbm_idx_mutex);
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for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {
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for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {
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cik_select_se_sh(rdev, i, j);
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@ -5842,7 +5827,6 @@ static void cik_wait_for_rlc_serdes(struct radeon_device *rdev)
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}
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}
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cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
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mutex_unlock(&rdev->grbm_idx_mutex);
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mask = SE_MASTER_BUSY_MASK | GC_MASTER_BUSY | TC0_MASTER_BUSY | TC1_MASTER_BUSY;
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for (k = 0; k < rdev->usec_timeout; k++) {
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@ -5977,12 +5961,10 @@ static int cik_rlc_resume(struct radeon_device *rdev)
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WREG32(RLC_LB_CNTR_INIT, 0);
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WREG32(RLC_LB_CNTR_MAX, 0x00008000);
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mutex_lock(&rdev->grbm_idx_mutex);
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cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
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WREG32(RLC_LB_INIT_CU_MASK, 0xffffffff);
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WREG32(RLC_LB_PARAMS, 0x00600408);
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WREG32(RLC_LB_CNTL, 0x80000004);
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mutex_unlock(&rdev->grbm_idx_mutex);
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WREG32(RLC_MC_CNTL, 0);
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WREG32(RLC_UCODE_CNTL, 0);
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@ -6049,13 +6031,11 @@ static void cik_enable_cgcg(struct radeon_device *rdev, bool enable)
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tmp = cik_halt_rlc(rdev);
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mutex_lock(&rdev->grbm_idx_mutex);
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cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
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WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
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WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
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tmp2 = BPM_ADDR_MASK | CGCG_OVERRIDE_0 | CGLS_ENABLE;
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WREG32(RLC_SERDES_WR_CTRL, tmp2);
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mutex_unlock(&rdev->grbm_idx_mutex);
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cik_update_rlc(rdev, tmp);
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@ -6098,13 +6078,11 @@ static void cik_enable_mgcg(struct radeon_device *rdev, bool enable)
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tmp = cik_halt_rlc(rdev);
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mutex_lock(&rdev->grbm_idx_mutex);
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cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
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WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
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WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
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data = BPM_ADDR_MASK | MGCG_OVERRIDE_0;
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WREG32(RLC_SERDES_WR_CTRL, data);
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mutex_unlock(&rdev->grbm_idx_mutex);
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cik_update_rlc(rdev, tmp);
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@ -6148,13 +6126,11 @@ static void cik_enable_mgcg(struct radeon_device *rdev, bool enable)
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tmp = cik_halt_rlc(rdev);
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mutex_lock(&rdev->grbm_idx_mutex);
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cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
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WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
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WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
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data = BPM_ADDR_MASK | MGCG_OVERRIDE_1;
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WREG32(RLC_SERDES_WR_CTRL, data);
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mutex_unlock(&rdev->grbm_idx_mutex);
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cik_update_rlc(rdev, tmp);
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}
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@ -6583,12 +6559,10 @@ static u32 cik_get_cu_active_bitmap(struct radeon_device *rdev, u32 se, u32 sh)
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u32 mask = 0, tmp, tmp1;
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int i;
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mutex_lock(&rdev->grbm_idx_mutex);
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cik_select_se_sh(rdev, se, sh);
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tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
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tmp1 = RREG32(GC_USER_SHADER_ARRAY_CONFIG);
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cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
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mutex_unlock(&rdev->grbm_idx_mutex);
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tmp &= 0xffff0000;
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@ -2442,8 +2442,6 @@ struct radeon_device {
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struct radeon_atcs atcs;
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/* srbm instance registers */
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struct mutex srbm_mutex;
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/* GRBM index mutex. Protects concurrents access to GRBM index */
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struct mutex grbm_idx_mutex;
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/* clock, powergating flags */
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u32 cg_flags;
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u32 pg_flags;
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@ -1341,7 +1341,6 @@ int radeon_device_init(struct radeon_device *rdev,
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mutex_init(&rdev->pm.mutex);
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mutex_init(&rdev->gpu_clock_mutex);
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mutex_init(&rdev->srbm_mutex);
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mutex_init(&rdev->grbm_idx_mutex);
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init_rwsem(&rdev->pm.mclk_lock);
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init_rwsem(&rdev->exclusive_lock);
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init_waitqueue_head(&rdev->irq.vblank_queue);
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