Merge branch 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull timer fixes from Thomas Gleixner: "A small set of fixes from the timer departement: - Add a missing timer wheel clock forward when migrating timers off a unplugged CPU to prevent operating on a stale clock base and missing timer deadlines. - Use the proper shift count to extract data from a register value to prevent evaluating unrelated bits - Make the error return check in the FSL timer driver work correctly. Checking an unsigned variable for less than zero does not really work well. - Clarify the confusing comments in the ARC timer code" * 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: timers: Forward timer base before migrating timers clocksource/drivers/arc_timer: Update some comments clocksource/drivers/mips-gic-timer: Use correct shift count to extract data clocksource/drivers/fsl_ftm_timer: Fix error return checking
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4c4ce3022d
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@ -251,9 +251,14 @@ static irqreturn_t timer_irq_handler(int irq, void *dev_id)
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int irq_reenable = clockevent_state_periodic(evt);
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/*
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* Any write to CTRL reg ACks the interrupt, we rewrite the
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* Count when [N]ot [H]alted bit.
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* And re-arm it if perioid by [I]nterrupt [E]nable bit
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* 1. ACK the interrupt
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* - For ARC700, any write to CTRL reg ACKs it, so just rewrite
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* Count when [N]ot [H]alted bit.
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* - For HS3x, it is a bit subtle. On taken count-down interrupt,
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* IP bit [3] is set, which needs to be cleared for ACK'ing.
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* The write below can only update the other two bits, hence
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* explicitly clears IP bit
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* 2. Re-arm interrupt if periodic by writing to IE bit [0]
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*/
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write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH);
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@ -281,7 +281,7 @@ static int __init __ftm_clk_init(struct device_node *np, char *cnt_name,
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static unsigned long __init ftm_clk_init(struct device_node *np)
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{
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unsigned long freq;
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long freq;
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freq = __ftm_clk_init(np, "ftm-evt-counter-en", "ftm-evt");
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if (freq <= 0)
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@ -166,7 +166,7 @@ static int __init __gic_clocksource_init(void)
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/* Set clocksource mask. */
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count_width = read_gic_config() & GIC_CONFIG_COUNTBITS;
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count_width >>= __fls(GIC_CONFIG_COUNTBITS);
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count_width >>= __ffs(GIC_CONFIG_COUNTBITS);
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count_width *= 4;
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count_width += 32;
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gic_clocksource.mask = CLOCKSOURCE_MASK(count_width);
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@ -1894,6 +1894,12 @@ int timers_dead_cpu(unsigned int cpu)
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raw_spin_lock_irq(&new_base->lock);
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raw_spin_lock_nested(&old_base->lock, SINGLE_DEPTH_NESTING);
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/*
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* The current CPUs base clock might be stale. Update it
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* before moving the timers over.
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*/
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forward_timer_base(new_base);
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BUG_ON(old_base->running_timer);
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for (i = 0; i < WHEEL_SIZE; i++)
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