IOMMU Fixes for Linux v5.4-rc1
A couple of fixes for the AMD IOMMU driver have piled up:
* Some fixes for the reworked IO page-table which caused memory
leaks or did not allow to downgrade mappings under some
conditions.
* Locking fixes to fix a couple of possible races around
accessing 'struct protection_domain'. The races got introduced
when the dma-ops path became lock-less in the fast-path.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEEr9jSbILcajRFYWYyK/BELZcBGuMFAl2PrpoACgkQK/BELZcB
GuNo6A/9EpxNUllqaPLvGYJYPN1ye2kx9QOCYZW6vo+at10X9ywf69IqYtjP9cSe
x5uWUy0BFjBhqHvMvQ+9m6begFsue/+csUZDmeP+KvBHwNxUOxFS/fb4P0WlmmNF
/zzsjQbt+r1FRIdYodH2CvBJKyuxNxou0W1aARvs9iggoXVG5Es+WG9+kwnixBE+
WB1gpuX0zKWlu31z2+i+JrVtdjMqoupfR/T40C4OsMD3NjfNi0bkCqmnqJ3CpNh9
RWPmNlnd29imPhMYQonZcUFD6Ru4NOUCfEFCjHEK/nk9kSHMYjgkKFgOzvA8h1xG
Nkzd0dRw39UMNYzKDGHHaE/xXRJV+kOFxZBcABnxfx2r+9EgXBD36AUOsfpeOdVi
9ab75ok7Ly+tkCgdK7sEeuDD0HJiZkUYT7BqMTdBOt64BK/GtRvepF1Zv15hG6Xn
imlAfyE4q+avTAJkrXeIu6IgdvF4XvorsIdeF5dKjCBTdTkj8DLXq/gejAo0g1NO
shOz9E2lde1IdeT+U580nZy9JmkKDFjyeG4QkwSz7Oln/gHIFQS1K8A4i30kGiok
vMsJzBidtUuqRWupwymtobCAggZE86O2XLOwnxolarJAFOqg5V2j7fSyL+XxXUDC
r85Ve/jtAhMho5594X72CumoNzzr0bDyCcGerzvT0wBRXcKLIsw=
=xajX
-----END PGP SIGNATURE-----
Merge tag 'iommu-fixes-5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
Pull iommu fixes from Joerg Roedel:
"A couple of fixes for the AMD IOMMU driver have piled up:
- Some fixes for the reworked IO page-table which caused memory leaks
or did not allow to downgrade mappings under some conditions.
- Locking fixes to fix a couple of possible races around accessing
'struct protection_domain'. The races got introduced when the
dma-ops path became lock-less in the fast-path"
* tag 'iommu-fixes-5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu:
iommu/amd: Lock code paths traversing protection_domain->dev_list
iommu/amd: Lock dev_data in attach/detach code paths
iommu/amd: Check for busy devices earlier in attach_device()
iommu/amd: Take domain->lock for complete attach/detach path
iommu/amd: Remove amd_iommu_devtable_lock
iommu/amd: Remove domain->updated
iommu/amd: Wait for completion of IOTLB flush in attach_device
iommu/amd: Unmap all L7 PTEs when downgrading page-sizes
iommu/amd: Introduce first_pte_l7() helper
iommu/amd: Fix downgrading default page-sizes in alloc_pte()
iommu/amd: Fix pages leak in free_pagetable()
This commit is contained in:
Linus Torvalds
commit
4d2af08ed0
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@ -70,7 +70,6 @@
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*/
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#define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
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static DEFINE_SPINLOCK(amd_iommu_devtable_lock);
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static DEFINE_SPINLOCK(pd_bitmap_lock);
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/* List of all available dev_data structures */
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@ -202,6 +201,7 @@ static struct iommu_dev_data *alloc_dev_data(u16 devid)
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if (!dev_data)
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return NULL;
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spin_lock_init(&dev_data->lock);
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dev_data->devid = devid;
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ratelimit_default_init(&dev_data->rs);
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@ -501,6 +501,29 @@ static void iommu_uninit_device(struct device *dev)
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*/
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}
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/*
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* Helper function to get the first pte of a large mapping
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*/
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static u64 *first_pte_l7(u64 *pte, unsigned long *page_size,
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unsigned long *count)
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{
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unsigned long pte_mask, pg_size, cnt;
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u64 *fpte;
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pg_size = PTE_PAGE_SIZE(*pte);
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cnt = PAGE_SIZE_PTE_COUNT(pg_size);
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pte_mask = ~((cnt << 3) - 1);
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fpte = (u64 *)(((unsigned long)pte) & pte_mask);
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if (page_size)
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*page_size = pg_size;
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if (count)
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*count = cnt;
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return fpte;
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}
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/****************************************************************************
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*
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* Interrupt handling functions
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@ -1311,8 +1334,12 @@ static void domain_flush_np_cache(struct protection_domain *domain,
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dma_addr_t iova, size_t size)
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{
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if (unlikely(amd_iommu_np_cache)) {
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unsigned long flags;
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spin_lock_irqsave(&domain->lock, flags);
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domain_flush_pages(domain, iova, size);
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domain_flush_complete(domain);
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spin_unlock_irqrestore(&domain->lock, flags);
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}
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}
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@ -1425,7 +1452,7 @@ static void free_pagetable(struct protection_domain *domain)
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BUG_ON(domain->mode < PAGE_MODE_NONE ||
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domain->mode > PAGE_MODE_6_LEVEL);
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free_sub_pt(root, domain->mode, freelist);
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freelist = free_sub_pt(root, domain->mode, freelist);
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free_page_list(freelist);
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}
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@ -1435,10 +1462,11 @@ static void free_pagetable(struct protection_domain *domain)
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* another level increases the size of the address space by 9 bits to a size up
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* to 64 bits.
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*/
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static void increase_address_space(struct protection_domain *domain,
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static bool increase_address_space(struct protection_domain *domain,
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gfp_t gfp)
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{
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unsigned long flags;
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bool ret = false;
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u64 *pte;
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spin_lock_irqsave(&domain->lock, flags);
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@ -1455,19 +1483,21 @@ static void increase_address_space(struct protection_domain *domain,
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iommu_virt_to_phys(domain->pt_root));
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domain->pt_root = pte;
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domain->mode += 1;
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domain->updated = true;
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ret = true;
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out:
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spin_unlock_irqrestore(&domain->lock, flags);
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return;
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return ret;
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}
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static u64 *alloc_pte(struct protection_domain *domain,
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unsigned long address,
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unsigned long page_size,
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u64 **pte_page,
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gfp_t gfp)
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gfp_t gfp,
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bool *updated)
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{
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int level, end_lvl;
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u64 *pte, *page;
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@ -1475,7 +1505,7 @@ static u64 *alloc_pte(struct protection_domain *domain,
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BUG_ON(!is_power_of_2(page_size));
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while (address > PM_LEVEL_SIZE(domain->mode))
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increase_address_space(domain, gfp);
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*updated = increase_address_space(domain, gfp) || *updated;
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level = domain->mode - 1;
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pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
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@ -1489,9 +1519,32 @@ static u64 *alloc_pte(struct protection_domain *domain,
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__pte = *pte;
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pte_level = PM_PTE_LEVEL(__pte);
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if (!IOMMU_PTE_PRESENT(__pte) ||
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/*
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* If we replace a series of large PTEs, we need
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* to tear down all of them.
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*/
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if (IOMMU_PTE_PRESENT(__pte) &&
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pte_level == PAGE_MODE_7_LEVEL) {
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unsigned long count, i;
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u64 *lpte;
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lpte = first_pte_l7(pte, NULL, &count);
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/*
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* Unmap the replicated PTEs that still match the
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* original large mapping
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*/
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for (i = 0; i < count; ++i)
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cmpxchg64(&lpte[i], __pte, 0ULL);
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*updated = true;
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continue;
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}
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if (!IOMMU_PTE_PRESENT(__pte) ||
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pte_level == PAGE_MODE_NONE) {
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page = (u64 *)get_zeroed_page(gfp);
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if (!page)
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return NULL;
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@ -1500,8 +1553,8 @@ static u64 *alloc_pte(struct protection_domain *domain,
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/* pte could have been changed somewhere. */
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if (cmpxchg64(pte, __pte, __npte) != __pte)
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free_page((unsigned long)page);
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else if (pte_level == PAGE_MODE_7_LEVEL)
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domain->updated = true;
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else if (IOMMU_PTE_PRESENT(__pte))
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*updated = true;
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continue;
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}
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@ -1566,17 +1619,12 @@ static u64 *fetch_pte(struct protection_domain *domain,
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*page_size = PTE_LEVEL_PAGE_SIZE(level);
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}
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if (PM_PTE_LEVEL(*pte) == 0x07) {
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unsigned long pte_mask;
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/*
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* If we have a series of large PTEs, make
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* sure to return a pointer to the first one.
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*/
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*page_size = pte_mask = PTE_PAGE_SIZE(*pte);
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pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
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pte = (u64 *)(((unsigned long)pte) & pte_mask);
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}
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/*
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* If we have a series of large PTEs, make
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* sure to return a pointer to the first one.
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*/
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if (PM_PTE_LEVEL(*pte) == PAGE_MODE_7_LEVEL)
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pte = first_pte_l7(pte, page_size, NULL);
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return pte;
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}
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@ -1615,26 +1663,29 @@ static int iommu_map_page(struct protection_domain *dom,
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gfp_t gfp)
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{
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struct page *freelist = NULL;
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bool updated = false;
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u64 __pte, *pte;
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int i, count;
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int ret, i, count;
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BUG_ON(!IS_ALIGNED(bus_addr, page_size));
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BUG_ON(!IS_ALIGNED(phys_addr, page_size));
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ret = -EINVAL;
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if (!(prot & IOMMU_PROT_MASK))
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return -EINVAL;
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goto out;
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count = PAGE_SIZE_PTE_COUNT(page_size);
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pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp);
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pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp, &updated);
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ret = -ENOMEM;
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if (!pte)
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return -ENOMEM;
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goto out;
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for (i = 0; i < count; ++i)
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freelist = free_clear_pte(&pte[i], pte[i], freelist);
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if (freelist != NULL)
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dom->updated = true;
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updated = true;
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if (count > 1) {
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__pte = PAGE_SIZE_PTE(__sme_set(phys_addr), page_size);
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@ -1650,12 +1701,21 @@ static int iommu_map_page(struct protection_domain *dom,
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for (i = 0; i < count; ++i)
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pte[i] = __pte;
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update_domain(dom);
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ret = 0;
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out:
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if (updated) {
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unsigned long flags;
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spin_lock_irqsave(&dom->lock, flags);
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update_domain(dom);
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spin_unlock_irqrestore(&dom->lock, flags);
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}
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/* Everything flushed out, free pages now */
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free_page_list(freelist);
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return 0;
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return ret;
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}
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static unsigned long iommu_unmap_page(struct protection_domain *dom,
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@ -1806,8 +1866,12 @@ static void free_gcr3_table(struct protection_domain *domain)
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static void dma_ops_domain_flush_tlb(struct dma_ops_domain *dom)
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{
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unsigned long flags;
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spin_lock_irqsave(&dom->domain.lock, flags);
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domain_flush_tlb(&dom->domain);
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domain_flush_complete(&dom->domain);
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spin_unlock_irqrestore(&dom->domain.lock, flags);
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}
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static void iova_domain_flush_tlb(struct iova_domain *iovad)
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@ -2022,36 +2086,6 @@ static void do_detach(struct iommu_dev_data *dev_data)
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domain->dev_cnt -= 1;
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}
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/*
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* If a device is not yet associated with a domain, this function makes the
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* device visible in the domain
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*/
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static int __attach_device(struct iommu_dev_data *dev_data,
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struct protection_domain *domain)
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{
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int ret;
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/* lock domain */
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spin_lock(&domain->lock);
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ret = -EBUSY;
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if (dev_data->domain != NULL)
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goto out_unlock;
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/* Attach alias group root */
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do_attach(dev_data, domain);
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ret = 0;
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out_unlock:
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/* ready */
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spin_unlock(&domain->lock);
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return ret;
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}
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static void pdev_iommuv2_disable(struct pci_dev *pdev)
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{
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pci_disable_ats(pdev);
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@ -2133,19 +2167,28 @@ static int attach_device(struct device *dev,
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unsigned long flags;
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int ret;
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spin_lock_irqsave(&domain->lock, flags);
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dev_data = get_dev_data(dev);
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spin_lock(&dev_data->lock);
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ret = -EBUSY;
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if (dev_data->domain != NULL)
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goto out;
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if (!dev_is_pci(dev))
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goto skip_ats_check;
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pdev = to_pci_dev(dev);
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if (domain->flags & PD_IOMMUV2_MASK) {
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ret = -EINVAL;
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if (!dev_data->passthrough)
|
||||
return -EINVAL;
|
||||
goto out;
|
||||
|
||||
if (dev_data->iommu_v2) {
|
||||
if (pdev_iommuv2_enable(pdev) != 0)
|
||||
return -EINVAL;
|
||||
goto out;
|
||||
|
||||
dev_data->ats.enabled = true;
|
||||
dev_data->ats.qdep = pci_ats_queue_depth(pdev);
|
||||
|
|
@ -2158,9 +2201,9 @@ static int attach_device(struct device *dev,
|
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}
|
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|
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skip_ats_check:
|
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spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
|
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ret = __attach_device(dev_data, domain);
|
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spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
|
||||
ret = 0;
|
||||
|
||||
do_attach(dev_data, domain);
|
||||
|
||||
/*
|
||||
* We might boot into a crash-kernel here. The crashed kernel
|
||||
|
|
@ -2169,25 +2212,16 @@ static int attach_device(struct device *dev,
|
|||
*/
|
||||
domain_flush_tlb_pde(domain);
|
||||
|
||||
domain_flush_complete(domain);
|
||||
|
||||
out:
|
||||
spin_unlock(&dev_data->lock);
|
||||
|
||||
spin_unlock_irqrestore(&domain->lock, flags);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* Removes a device from a protection domain (unlocked)
|
||||
*/
|
||||
static void __detach_device(struct iommu_dev_data *dev_data)
|
||||
{
|
||||
struct protection_domain *domain;
|
||||
|
||||
domain = dev_data->domain;
|
||||
|
||||
spin_lock(&domain->lock);
|
||||
|
||||
do_detach(dev_data);
|
||||
|
||||
spin_unlock(&domain->lock);
|
||||
}
|
||||
|
||||
/*
|
||||
* Removes a device from a protection domain (with devtable_lock held)
|
||||
*/
|
||||
|
|
@ -2200,6 +2234,10 @@ static void detach_device(struct device *dev)
|
|||
dev_data = get_dev_data(dev);
|
||||
domain = dev_data->domain;
|
||||
|
||||
spin_lock_irqsave(&domain->lock, flags);
|
||||
|
||||
spin_lock(&dev_data->lock);
|
||||
|
||||
/*
|
||||
* First check if the device is still attached. It might already
|
||||
* be detached from its domain because the generic
|
||||
|
|
@ -2207,15 +2245,12 @@ static void detach_device(struct device *dev)
|
|||
* our alias handling.
|
||||
*/
|
||||
if (WARN_ON(!dev_data->domain))
|
||||
return;
|
||||
goto out;
|
||||
|
||||
/* lock device table */
|
||||
spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
|
||||
__detach_device(dev_data);
|
||||
spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
|
||||
do_detach(dev_data);
|
||||
|
||||
if (!dev_is_pci(dev))
|
||||
return;
|
||||
goto out;
|
||||
|
||||
if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
|
||||
pdev_iommuv2_disable(to_pci_dev(dev));
|
||||
|
|
@ -2223,6 +2258,11 @@ static void detach_device(struct device *dev)
|
|||
pci_disable_ats(to_pci_dev(dev));
|
||||
|
||||
dev_data->ats.enabled = false;
|
||||
|
||||
out:
|
||||
spin_unlock(&dev_data->lock);
|
||||
|
||||
spin_unlock_irqrestore(&domain->lock, flags);
|
||||
}
|
||||
|
||||
static int amd_iommu_add_device(struct device *dev)
|
||||
|
|
@ -2354,15 +2394,10 @@ static void update_device_table(struct protection_domain *domain)
|
|||
|
||||
static void update_domain(struct protection_domain *domain)
|
||||
{
|
||||
if (!domain->updated)
|
||||
return;
|
||||
|
||||
update_device_table(domain);
|
||||
|
||||
domain_flush_devices(domain);
|
||||
domain_flush_tlb_pde(domain);
|
||||
|
||||
domain->updated = false;
|
||||
}
|
||||
|
||||
static int dir2prot(enum dma_data_direction direction)
|
||||
|
|
@ -2392,6 +2427,7 @@ static dma_addr_t __map_single(struct device *dev,
|
|||
{
|
||||
dma_addr_t offset = paddr & ~PAGE_MASK;
|
||||
dma_addr_t address, start, ret;
|
||||
unsigned long flags;
|
||||
unsigned int pages;
|
||||
int prot = 0;
|
||||
int i;
|
||||
|
|
@ -2429,8 +2465,10 @@ static dma_addr_t __map_single(struct device *dev,
|
|||
iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
|
||||
}
|
||||
|
||||
spin_lock_irqsave(&dma_dom->domain.lock, flags);
|
||||
domain_flush_tlb(&dma_dom->domain);
|
||||
domain_flush_complete(&dma_dom->domain);
|
||||
spin_unlock_irqrestore(&dma_dom->domain.lock, flags);
|
||||
|
||||
dma_ops_free_iova(dma_dom, address, pages);
|
||||
|
||||
|
|
@ -2459,8 +2497,12 @@ static void __unmap_single(struct dma_ops_domain *dma_dom,
|
|||
}
|
||||
|
||||
if (amd_iommu_unmap_flush) {
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&dma_dom->domain.lock, flags);
|
||||
domain_flush_tlb(&dma_dom->domain);
|
||||
domain_flush_complete(&dma_dom->domain);
|
||||
spin_unlock_irqrestore(&dma_dom->domain.lock, flags);
|
||||
dma_ops_free_iova(dma_dom, dma_addr, pages);
|
||||
} else {
|
||||
pages = __roundup_pow_of_two(pages);
|
||||
|
|
@ -2866,16 +2908,16 @@ static void cleanup_domain(struct protection_domain *domain)
|
|||
struct iommu_dev_data *entry;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
|
||||
spin_lock_irqsave(&domain->lock, flags);
|
||||
|
||||
while (!list_empty(&domain->dev_list)) {
|
||||
entry = list_first_entry(&domain->dev_list,
|
||||
struct iommu_dev_data, list);
|
||||
BUG_ON(!entry->domain);
|
||||
__detach_device(entry);
|
||||
do_detach(entry);
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
|
||||
spin_unlock_irqrestore(&domain->lock, flags);
|
||||
}
|
||||
|
||||
static void protection_domain_free(struct protection_domain *domain)
|
||||
|
|
@ -3226,9 +3268,12 @@ static bool amd_iommu_is_attach_deferred(struct iommu_domain *domain,
|
|||
static void amd_iommu_flush_iotlb_all(struct iommu_domain *domain)
|
||||
{
|
||||
struct protection_domain *dom = to_pdomain(domain);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&dom->lock, flags);
|
||||
domain_flush_tlb_pde(dom);
|
||||
domain_flush_complete(dom);
|
||||
spin_unlock_irqrestore(&dom->lock, flags);
|
||||
}
|
||||
|
||||
static void amd_iommu_iotlb_sync(struct iommu_domain *domain,
|
||||
|
|
@ -3290,7 +3335,6 @@ void amd_iommu_domain_direct_map(struct iommu_domain *dom)
|
|||
|
||||
/* Update data structure */
|
||||
domain->mode = PAGE_MODE_NONE;
|
||||
domain->updated = true;
|
||||
|
||||
/* Make changes visible to IOMMUs */
|
||||
update_domain(domain);
|
||||
|
|
@ -3336,7 +3380,6 @@ int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
|
|||
|
||||
domain->glx = levels;
|
||||
domain->flags |= PD_IOMMUV2_MASK;
|
||||
domain->updated = true;
|
||||
|
||||
update_domain(domain);
|
||||
|
||||
|
|
|
|||
|
|
@ -475,7 +475,6 @@ struct protection_domain {
|
|||
int glx; /* Number of levels for GCR3 table */
|
||||
u64 *gcr3_tbl; /* Guest CR3 table */
|
||||
unsigned long flags; /* flags to find out type of domain */
|
||||
bool updated; /* complete domain flush required */
|
||||
unsigned dev_cnt; /* devices assigned to this domain */
|
||||
unsigned dev_iommu[MAX_IOMMUS]; /* per-IOMMU reference count */
|
||||
};
|
||||
|
|
@ -634,6 +633,9 @@ struct devid_map {
|
|||
* This struct contains device specific data for the IOMMU
|
||||
*/
|
||||
struct iommu_dev_data {
|
||||
/*Protect against attach/detach races */
|
||||
spinlock_t lock;
|
||||
|
||||
struct list_head list; /* For domain->dev_list */
|
||||
struct llist_node dev_data_list; /* For global dev_data_list */
|
||||
struct protection_domain *domain; /* Domain the device is bound to */
|
||||
|
|
|
|||
Loading…
Reference in New Issue