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Merge branch 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull irq fixes from Thomas Gleixner:
 "From the irqchip departement you get:

   - regression fix for omap-intc

   - regression fix for atmel-aic-common

   - functional correctness fix for hip04

   - type mismatch fix for gic-v3-its

   - proper error pointer check for mtd-sysirq

  Mostly one and two liners except for the omap regression fix which is
  slightly larger than desired"

* 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  irqchip: atmel-aic-common: Prevent clobbering of priority when changing IRQ type
  irqchip: omap-intc: Fix legacy DMA regression
  irqchip: gic-v3-its: Fix use of max with decimal constant
  irqchip: hip04: Initialize hip04_cpu_map to 0xffff
  irqchip: mtk-sysirq: Use IS_ERR() instead of NULL pointer check
This commit is contained in:
Linus Torvalds 2015-01-25 18:07:01 -08:00
parent b73f0c8f4b 2f5eaf66e5
commit 4d2f0ef1c9
5 changed files with 27 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/irqchip/irq-atmel-aic-common.c
View File

@ -28,7 +28,7 @@
#define AT91_AIC_IRQ_MIN_PRIORITY 0 #define AT91_AIC_IRQ_MIN_PRIORITY 0
#define AT91_AIC_IRQ_MAX_PRIORITY 7 #define AT91_AIC_IRQ_MAX_PRIORITY 7
#define AT91_AIC_SRCTYPE GENMASK(7, 6) #define AT91_AIC_SRCTYPE GENMASK(6, 5)
#define AT91_AIC_SRCTYPE_LOW (0 << 5) #define AT91_AIC_SRCTYPE_LOW (0 << 5)
#define AT91_AIC_SRCTYPE_FALLING (1 << 5) #define AT91_AIC_SRCTYPE_FALLING (1 << 5)
#define AT91_AIC_SRCTYPE_HIGH (2 << 5) #define AT91_AIC_SRCTYPE_HIGH (2 << 5)
@ -74,7 +74,7 @@ int aic_common_set_type(struct irq_data *d, unsigned type, unsigned *val)
return -EINVAL; return -EINVAL;
} }
*val &= AT91_AIC_SRCTYPE; *val &= ~AT91_AIC_SRCTYPE;
*val |= aic_type; *val |= aic_type;
return 0; return 0;

2
drivers/irqchip/irq-gic-v3-its.c
View File

@ -1053,7 +1053,7 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
* of two entries. No, the architecture doesn't let you * of two entries. No, the architecture doesn't let you
* express an ITT with a single entry. * express an ITT with a single entry.
*/ */
nr_ites = max(2, roundup_pow_of_two(nvecs)); nr_ites = max(2UL, roundup_pow_of_two(nvecs));
sz = nr_ites * its->ite_size; sz = nr_ites * its->ite_size;
sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1; sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
itt = kmalloc(sz, GFP_KERNEL); itt = kmalloc(sz, GFP_KERNEL);

2
drivers/irqchip/irq-hip04.c
View File

@ -381,7 +381,7 @@ hip04_of_init(struct device_node *node, struct device_node *parent)
* It will be refined as each CPU probes its ID. * It will be refined as each CPU probes its ID.
*/ */
for (i = 0; i < NR_HIP04_CPU_IF; i++) for (i = 0; i < NR_HIP04_CPU_IF; i++)
hip04_cpu_map[i] = 0xff; hip04_cpu_map[i] = 0xffff;
/* /*
* Find out how many interrupts are supported. * Find out how many interrupts are supported.

4
drivers/irqchip/irq-mtk-sysirq.c
View File

@ -137,9 +137,9 @@ static int __init mtk_sysirq_of_init(struct device_node *node,
return -ENOMEM; return -ENOMEM;
chip_data->intpol_base = of_io_request_and_map(node, 0, "intpol"); chip_data->intpol_base = of_io_request_and_map(node, 0, "intpol");
if (!chip_data->intpol_base) { if (IS_ERR(chip_data->intpol_base)) {
pr_err("mtk_sysirq: unable to map sysirq register\n"); pr_err("mtk_sysirq: unable to map sysirq register\n");
ret = -ENOMEM; ret = PTR_ERR(chip_data->intpol_base);
goto out_free; goto out_free;
} }

26
drivers/irqchip/irq-omap-intc.c
View File

@ -263,7 +263,7 @@ static int __init omap_init_irq_of(struct device_node *node)
return ret; return ret;
} }
static int __init omap_init_irq_legacy(u32 base) static int __init omap_init_irq_legacy(u32 base, struct device_node *node)
{ {
int j, irq_base; int j, irq_base;
@ -277,7 +277,7 @@ static int __init omap_init_irq_legacy(u32 base)
irq_base = 0; irq_base = 0;
} }
domain = irq_domain_add_legacy(NULL, omap_nr_irqs, irq_base, 0, domain = irq_domain_add_legacy(node, omap_nr_irqs, irq_base, 0,
&irq_domain_simple_ops, NULL); &irq_domain_simple_ops, NULL);
omap_irq_soft_reset(); omap_irq_soft_reset();
@ -301,10 +301,26 @@ static int __init omap_init_irq(u32 base, struct device_node *node)
{ {
int ret; int ret;
if (node) /*
* FIXME legacy OMAP DMA driver sitting under arch/arm/plat-omap/dma.c
* depends is still not ready for linear IRQ domains; because of that
* we need to temporarily "blacklist" OMAP2 and OMAP3 devices from using
* linear IRQ Domain until that driver is finally fixed.
*/
if (of_device_is_compatible(node, "ti,omap2-intc") ||
of_device_is_compatible(node, "ti,omap3-intc")) {
struct resource res;
if (of_address_to_resource(node, 0, &res))
return -ENOMEM;
base = res.start;
ret = omap_init_irq_legacy(base, node);
} else if (node) {
ret = omap_init_irq_of(node); ret = omap_init_irq_of(node);
else } else {
ret = omap_init_irq_legacy(base); ret = omap_init_irq_legacy(base, NULL);
}
if (ret == 0) if (ret == 0)
omap_irq_enable_protection(); omap_irq_enable_protection();