powerpc/64s: Avoid r3 save/restore in SLB miss handler
The SLB miss handler uses r3 for the faulting address but r12 is mostly able to be freed up to save r3 in. It just requires SRR1 be reloaded again on error. It would be more conventional to use r12 for SRR1 (and use r11 to save r3), but slb_allocate_realmode clobbers r11 and not r12. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Nicholas Piggin
Michael Ellerman
parent
fe5482c043
commit
4d7cd3b956
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@ -510,9 +510,9 @@ EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80)
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SET_SCRATCH0(r13)
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EXCEPTION_PROLOG_0(PACA_EXSLB)
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EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x380)
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std r3,PACA_EXSLB+EX_R3(r13)
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mr r12,r3 /* save r3 */
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mfspr r3,SPRN_DAR
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mfspr r12,SPRN_SRR1
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mfspr r11,SPRN_SRR1
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crset 4*cr6+eq
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#ifndef CONFIG_RELOCATABLE
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b slb_miss_realmode
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@ -532,9 +532,9 @@ EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80)
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SET_SCRATCH0(r13)
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EXCEPTION_PROLOG_0(PACA_EXSLB)
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EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x380)
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std r3,PACA_EXSLB+EX_R3(r13)
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mr r12,r3 /* save r3 */
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mfspr r3,SPRN_DAR
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mfspr r12,SPRN_SRR1
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mfspr r11,SPRN_SRR1
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crset 4*cr6+eq
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#ifndef CONFIG_RELOCATABLE
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b slb_miss_realmode
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@ -576,9 +576,9 @@ EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x80)
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SET_SCRATCH0(r13)
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EXCEPTION_PROLOG_0(PACA_EXSLB)
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EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x480)
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std r3,PACA_EXSLB+EX_R3(r13)
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mr r12,r3 /* save r3 */
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mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
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mfspr r12,SPRN_SRR1
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mfspr r11,SPRN_SRR1
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crclr 4*cr6+eq
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#ifndef CONFIG_RELOCATABLE
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b slb_miss_realmode
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@ -593,9 +593,9 @@ EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x80)
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SET_SCRATCH0(r13)
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EXCEPTION_PROLOG_0(PACA_EXSLB)
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EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x480)
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std r3,PACA_EXSLB+EX_R3(r13)
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mr r12,r3 /* save r3 */
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mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
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mfspr r12,SPRN_SRR1
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mfspr r11,SPRN_SRR1
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crclr 4*cr6+eq
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#ifndef CONFIG_RELOCATABLE
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b slb_miss_realmode
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@ -612,10 +612,10 @@ TRAMP_KVM(PACA_EXSLB, 0x480)
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EXC_COMMON_BEGIN(slb_miss_realmode)
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/*
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* r13 points to the PACA, r9 contains the saved CR,
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* r12 contain the saved SRR1, SRR0 is still ready for return
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* r12 contains the saved r3,
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* r11 contain the saved SRR1, SRR0 is still ready for return
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* r3 has the faulting address
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* r9 - r13 are saved in paca->exslb.
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* r3 is saved in paca->slb_r3
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* cr6.eq is set for a D-SLB miss, clear for a I-SLB miss
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* We assume we aren't going to take any exceptions during this
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* procedure.
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@ -624,6 +624,15 @@ EXC_COMMON_BEGIN(slb_miss_realmode)
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stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
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std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
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/*
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* Test MSR_RI before calling slb_allocate_realmode, because the
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* MSR in r11 gets clobbered. However we still want to allocate
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* SLB in case MSR_RI=0, to minimise the risk of getting stuck in
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* recursive SLB faults. So use cr5 for this, which is preserved.
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*/
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andi. r11,r11,MSR_RI /* check for unrecoverable exception */
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cmpdi cr5,r11,MSR_RI
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crset 4*cr0+eq
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#ifdef CONFIG_PPC_STD_MMU_64
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BEGIN_MMU_FTR_SECTION
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@ -637,21 +646,21 @@ END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX)
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beq- 8f /* if bad address, make full stack frame */
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andi. r10,r12,MSR_RI /* check for unrecoverable exception */
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beq- 2f
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bne- cr5,2f /* if unrecoverable exception, oops */
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/* All done -- return from exception. */
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.machine push
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.machine "power4"
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mtcrf 0x80,r9
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mtcrf 0x04,r9 /* MSR[RI] indication is in cr5 */
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mtcrf 0x02,r9 /* I/D indication is in cr6 */
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mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
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.machine pop
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RESTORE_CTR(r9, PACA_EXSLB)
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RESTORE_PPR_PACA(PACA_EXSLB, r9)
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ld r3,PACA_EXSLB+EX_R3(r13)
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mr r3,r12
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ld r9,PACA_EXSLB+EX_R9(r13)
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ld r10,PACA_EXSLB+EX_R10(r13)
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ld r11,PACA_EXSLB+EX_R11(r13)
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@ -661,8 +670,9 @@ END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX)
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b . /* prevent speculative execution */
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2: std r3,PACA_EXSLB+EX_DAR(r13)
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ld r3,PACA_EXSLB+EX_R3(r13)
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mr r3,r12
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mfspr r11,SPRN_SRR0
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mfspr r12,SPRN_SRR1
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LOAD_HANDLER(r10,unrecov_slb)
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mtspr SPRN_SRR0,r10
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ld r10,PACAKMSR(r13)
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@ -671,8 +681,9 @@ END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX)
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b .
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8: std r3,PACA_EXSLB+EX_DAR(r13)
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ld r3,PACA_EXSLB+EX_R3(r13)
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mr r3,r12
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mfspr r11,SPRN_SRR0
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mfspr r12,SPRN_SRR1
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LOAD_HANDLER(r10,bad_addr_slb)
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mtspr SPRN_SRR0,r10
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ld r10,PACAKMSR(r13)
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