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ASoC: fsl_ssi: Define ternary macros to simplify code 

Some regmap code looks redudant. So simplify it.

Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
Tested-by: Maciej S. Szmigiero <mail@maciej.szmigiero.name>
Reviewed-by: Maciej S. Szmigiero <mail@maciej.szmigiero.name>
Acked-by: Timur Tabi <timur@tabi.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Nicolin Chen 2017-12-17 18:52:10 -08:00 committed by Mark Brown
parent 8bc84a3344
commit 52eee84e81
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
2 changed files with 15 additions and 16 deletions
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27
sound/soc/fsl/fsl_ssi.c
View File

@ -408,13 +408,10 @@ static void fsl_ssi_rxtx_config(struct fsl_ssi *ssi, bool enable)
*/ */
static void fsl_ssi_fifo_clear(struct fsl_ssi *ssi, bool is_rx) static void fsl_ssi_fifo_clear(struct fsl_ssi *ssi, bool is_rx)
{ {
if (is_rx) { bool tx = !is_rx;
regmap_update_bits(ssi->regs, REG_SSI_SOR,
SSI_SOR_RX_CLR, SSI_SOR_RX_CLR); regmap_update_bits(ssi->regs, REG_SSI_SOR,
} else { SSI_SOR_xX_CLR(tx), SSI_SOR_xX_CLR(tx));
regmap_update_bits(ssi->regs, REG_SSI_SOR,
SSI_SOR_TX_CLR, SSI_SOR_TX_CLR);
}
} }
/** /**
@ -681,6 +678,7 @@ static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai, struct snd_soc_dai *dai,
struct snd_pcm_hw_params *hw_params) struct snd_pcm_hw_params *hw_params)
{ {
bool tx2, tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai); struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
struct regmap *regs = ssi->regs; struct regmap *regs = ssi->regs;
int synchronous = ssi->cpu_dai_drv.symmetric_rates, ret; int synchronous = ssi->cpu_dai_drv.symmetric_rates, ret;
@ -768,10 +766,9 @@ static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
(psr ? SSI_SxCCR_PSR : 0); (psr ? SSI_SxCCR_PSR : 0);
mask = SSI_SxCCR_PM_MASK | SSI_SxCCR_DIV2 | SSI_SxCCR_PSR; mask = SSI_SxCCR_PM_MASK | SSI_SxCCR_DIV2 | SSI_SxCCR_PSR;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || synchronous) /* STCCR is used for RX in synchronous mode */
regmap_update_bits(regs, REG_SSI_STCCR, mask, stccr); tx2 = tx || synchronous;
else regmap_update_bits(regs, REG_SSI_SxCCR(tx2), mask, stccr);
regmap_update_bits(regs, REG_SSI_SRCCR, mask, stccr);
if (!baudclk_is_used) { if (!baudclk_is_used) {
ret = clk_set_rate(ssi->baudclk, baudrate); ret = clk_set_rate(ssi->baudclk, baudrate);
@ -799,6 +796,7 @@ static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *hw_params, struct snd_pcm_hw_params *hw_params,
struct snd_soc_dai *dai) struct snd_soc_dai *dai)
{ {
bool tx2, tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai); struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
struct regmap *regs = ssi->regs; struct regmap *regs = ssi->regs;
unsigned int channels = params_channels(hw_params); unsigned int channels = params_channels(hw_params);
@ -849,11 +847,8 @@ static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
} }
/* In synchronous mode, the SSI uses STCCR for capture */ /* In synchronous mode, the SSI uses STCCR for capture */
if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) || tx2 = tx || ssi->cpu_dai_drv.symmetric_rates;
ssi->cpu_dai_drv.symmetric_rates) regmap_update_bits(regs, REG_SSI_SxCCR(tx2), SSI_SxCCR_WL_MASK, wl);
regmap_update_bits(regs, REG_SSI_STCCR, SSI_SxCCR_WL_MASK, wl);
else
regmap_update_bits(regs, REG_SSI_SRCCR, SSI_SxCCR_WL_MASK, wl);
return 0; return 0;
} }

4
sound/soc/fsl/fsl_ssi.h
View File

@ -35,10 +35,12 @@
#define REG_SSI_STCR 0x1c #define REG_SSI_STCR 0x1c
/* SSI Receive Configuration Register */ /* SSI Receive Configuration Register */
#define REG_SSI_SRCR 0x20 #define REG_SSI_SRCR 0x20
#define REG_SSI_SxCR(tx) ((tx) ? REG_SSI_STCR : REG_SSI_SRCR)
/* SSI Transmit Clock Control Register */ /* SSI Transmit Clock Control Register */
#define REG_SSI_STCCR 0x24 #define REG_SSI_STCCR 0x24
/* SSI Receive Clock Control Register */ /* SSI Receive Clock Control Register */
#define REG_SSI_SRCCR 0x28 #define REG_SSI_SRCCR 0x28
#define REG_SSI_SxCCR(tx) ((tx) ? REG_SSI_STCCR : REG_SSI_SRCCR)
/* SSI FIFO Control/Status Register */ /* SSI FIFO Control/Status Register */
#define REG_SSI_SFCSR 0x2c #define REG_SSI_SFCSR 0x2c
/* /*
@ -67,6 +69,7 @@
#define REG_SSI_STMSK 0x48 #define REG_SSI_STMSK 0x48
/* SSI Receive Time Slot Mask Register */ /* SSI Receive Time Slot Mask Register */
#define REG_SSI_SRMSK 0x4c #define REG_SSI_SRMSK 0x4c
#define REG_SSI_SxMSK(tx) ((tx) ? REG_SSI_STMSK : REG_SSI_SRMSK)
/* /*
* SSI AC97 Channel Status Register * SSI AC97 Channel Status Register
* *
@ -249,6 +252,7 @@
#define SSI_SOR_CLKOFF 0x00000040 #define SSI_SOR_CLKOFF 0x00000040
#define SSI_SOR_RX_CLR 0x00000020 #define SSI_SOR_RX_CLR 0x00000020
#define SSI_SOR_TX_CLR 0x00000010 #define SSI_SOR_TX_CLR 0x00000010
#define SSI_SOR_xX_CLR(tx) ((tx) ? SSI_SOR_TX_CLR : SSI_SOR_RX_CLR)
#define SSI_SOR_INIT 0x00000008 #define SSI_SOR_INIT 0x00000008
#define SSI_SOR_WAIT_SHIFT 1 #define SSI_SOR_WAIT_SHIFT 1
#define SSI_SOR_WAIT_MASK 0x00000006 #define SSI_SOR_WAIT_MASK 0x00000006