Merge branch 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 CPU updates from Ingo Molnar:
"The changes in this development cycle were:
- AMD CPU topology enhancements that are cleanups on current CPUs but
which enable future Fam17 hardware. (Yazen Ghannam)
- unify bugs.c and bugs_64.c (Borislav Petkov)
- remove the show_msr= boot option (Borislav Petkov)
- simplify a boot message (Borislav Petkov)"
* 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/cpu/AMD: Clean up cpu_llc_id assignment per topology feature
x86/cpu: Get rid of the show_msr= boot option
x86/cpu: Merge bugs.c and bugs_64.c
x86/cpu: Remove the printk format specifier in "CPU0: "
This commit is contained in:
Linus Torvalds
commit
535b2f73f6
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@ -3826,12 +3826,6 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
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shapers= [NET]
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Maximal number of shapers.
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show_msr= [x86] show boot-time MSR settings
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Format: { <integer> }
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Show boot-time (BIOS-initialized) MSR settings.
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The parameter means the number of CPUs to show,
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for example 1 means boot CPU only.
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simeth= [IA-64]
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simscsi=
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@ -20,13 +20,11 @@ obj-y := intel_cacheinfo.o scattered.o topology.o
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obj-y += common.o
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obj-y += rdrand.o
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obj-y += match.o
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obj-y += bugs.o
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obj-$(CONFIG_PROC_FS) += proc.o
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obj-$(CONFIG_X86_FEATURE_NAMES) += capflags.o powerflags.o
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obj-$(CONFIG_X86_32) += bugs.o
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obj-$(CONFIG_X86_64) += bugs_64.o
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obj-$(CONFIG_CPU_SUP_INTEL) += intel.o
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obj-$(CONFIG_CPU_SUP_AMD) += amd.o
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obj-$(CONFIG_CPU_SUP_CYRIX_32) += cyrix.o
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@ -314,11 +314,30 @@ static void amd_get_topology(struct cpuinfo_x86 *c)
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smp_num_siblings = ((ebx >> 8) & 3) + 1;
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c->x86_max_cores /= smp_num_siblings;
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c->cpu_core_id = ebx & 0xff;
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/*
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* We may have multiple LLCs if L3 caches exist, so check if we
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* have an L3 cache by looking at the L3 cache CPUID leaf.
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*/
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if (cpuid_edx(0x80000006)) {
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if (c->x86 == 0x17) {
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/*
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* LLC is at the core complex level.
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* Core complex id is ApicId[3].
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*/
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per_cpu(cpu_llc_id, cpu) = c->apicid >> 3;
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} else {
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/* LLC is at the node level. */
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per_cpu(cpu_llc_id, cpu) = node_id;
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}
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}
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} else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
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u64 value;
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rdmsrl(MSR_FAM10H_NODE_ID, value);
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node_id = value & 7;
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per_cpu(cpu_llc_id, cpu) = node_id;
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} else
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return;
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@ -329,9 +348,6 @@ static void amd_get_topology(struct cpuinfo_x86 *c)
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set_cpu_cap(c, X86_FEATURE_AMD_DCM);
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cus_per_node = c->x86_max_cores / nodes_per_socket;
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/* store NodeID, use llc_shared_map to store sibling info */
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per_cpu(cpu_llc_id, cpu) = node_id;
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/* core id has to be in the [0 .. cores_per_node - 1] range */
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c->cpu_core_id %= cus_per_node;
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}
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@ -356,15 +372,6 @@ static void amd_detect_cmp(struct cpuinfo_x86 *c)
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/* use socket ID also for last level cache */
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per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
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amd_get_topology(c);
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/*
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* Fix percpu cpu_llc_id here as LLC topology is different
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* for Fam17h systems.
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*/
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if (c->x86 != 0x17 || !cpuid_edx(0x80000006))
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return;
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per_cpu(cpu_llc_id, cpu) = c->apicid >> 3;
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#endif
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}
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@ -16,15 +16,19 @@
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#include <asm/msr.h>
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#include <asm/paravirt.h>
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#include <asm/alternative.h>
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#include <asm/pgtable.h>
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#include <asm/cacheflush.h>
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void __init check_bugs(void)
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{
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identify_boot_cpu();
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#ifndef CONFIG_SMP
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pr_info("CPU: ");
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print_cpu_info(&boot_cpu_data);
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#endif
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if (!IS_ENABLED(CONFIG_SMP)) {
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pr_info("CPU: ");
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print_cpu_info(&boot_cpu_data);
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}
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#ifdef CONFIG_X86_32
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/*
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* Check whether we are able to run this kernel safely on SMP.
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*
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@ -40,4 +44,18 @@ void __init check_bugs(void)
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alternative_instructions();
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fpu__init_check_bugs();
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#else /* CONFIG_X86_64 */
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alternative_instructions();
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/*
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* Make sure the first 2MB area is not mapped by huge pages
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* There are typically fixed size MTRRs in there and overlapping
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* MTRRs into large pages causes slow downs.
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*
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* Right now we don't do that with gbpages because there seems
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* very little benefit for that case.
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*/
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if (!direct_gbpages)
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set_memory_4k((unsigned long)__va(0), 1);
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#endif
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}
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@ -1,33 +0,0 @@
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/*
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* Copyright (C) 1994 Linus Torvalds
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* Copyright (C) 2000 SuSE
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <asm/alternative.h>
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#include <asm/bugs.h>
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#include <asm/processor.h>
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#include <asm/mtrr.h>
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#include <asm/cacheflush.h>
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void __init check_bugs(void)
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{
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identify_boot_cpu();
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#if !defined(CONFIG_SMP)
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pr_info("CPU: ");
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print_cpu_info(&boot_cpu_data);
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#endif
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alternative_instructions();
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/*
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* Make sure the first 2MB area is not mapped by huge pages
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* There are typically fixed size MTRRs in there and overlapping
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* MTRRs into large pages causes slow downs.
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*
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* Right now we don't do that with gbpages because there seems
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* very little benefit for that case.
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*/
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if (!direct_gbpages)
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set_memory_4k((unsigned long)__va(0), 1);
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}
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@ -1190,51 +1190,6 @@ void identify_secondary_cpu(struct cpuinfo_x86 *c)
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mtrr_ap_init();
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}
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struct msr_range {
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unsigned min;
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unsigned max;
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};
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static const struct msr_range msr_range_array[] = {
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{ 0x00000000, 0x00000418},
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{ 0xc0000000, 0xc000040b},
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{ 0xc0010000, 0xc0010142},
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{ 0xc0011000, 0xc001103b},
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};
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static void __print_cpu_msr(void)
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{
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unsigned index_min, index_max;
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unsigned index;
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u64 val;
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int i;
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for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
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index_min = msr_range_array[i].min;
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index_max = msr_range_array[i].max;
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for (index = index_min; index < index_max; index++) {
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if (rdmsrl_safe(index, &val))
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continue;
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pr_info(" MSR%08x: %016llx\n", index, val);
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}
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}
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}
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static int show_msr;
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static __init int setup_show_msr(char *arg)
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{
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int num;
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get_option(&arg, &num);
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if (num > 0)
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show_msr = num;
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return 1;
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}
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__setup("show_msr=", setup_show_msr);
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static __init int setup_noclflush(char *arg)
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{
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setup_clear_cpu_cap(X86_FEATURE_CLFLUSH);
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@ -1268,14 +1223,6 @@ void print_cpu_info(struct cpuinfo_x86 *c)
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pr_cont(", stepping: 0x%x)\n", c->x86_mask);
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else
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pr_cont(")\n");
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print_cpu_msr(c);
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}
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void print_cpu_msr(struct cpuinfo_x86 *c)
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{
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if (c->cpu_index < show_msr)
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__print_cpu_msr();
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}
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static __init int setup_disablecpuid(char *arg)
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@ -1352,7 +1352,7 @@ void __init native_smp_prepare_cpus(unsigned int max_cpus)
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default_setup_apic_routing();
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cpu0_logical_apicid = apic_bsp_setup(false);
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pr_info("CPU%d: ", 0);
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pr_info("CPU0: ");
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print_cpu_info(&cpu_data(0));
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if (is_uv_system())
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