arm[64] perf updates for 4.5:
- Support for the CPU PMU in Cortex-A72
- Add sysfs entries to describe the architected events and their
mappings for PMUv{1-3}
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Merge tag 'arm64-perf' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
Pull arm[64] perf updates from Will Deacon:
"In the past, I have funnelled perf updates through the respective
architecture trees, but now that the arm/arm64 perf driver has been
largely consolidated under drivers/perf/, it makes more sense to send
a separate pull, particularly as I'm listed as maintainer for all the
files involved. I offered the branch to arm-soc, but Arnd suggested
that I just send it to you directly.
So, here is the arm/arm64 perf queue for 4.5. The main features are
described below, but the most useful change is from Drew, which
advertises our architected event mapping in sysfs so that the perf
tool is a lot more user friendly and no longer requires the use of
magic hex constants for profiling common events.
- Support for the CPU PMU in Cortex-A72
- Add sysfs entries to describe the architected events and their
mappings for PMUv{1-3}"
* tag 'arm64-perf' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
arm64: perf: add support for Cortex-A72
arm64: perf: add format entry to describe event -> config mapping
ARM: perf: add format entry to describe event -> config mapping
arm64: kernel: enforce pmuserenr_el0 initialization and restore
arm64: perf: Correct Cortex-A53/A57 compatible values
arm64: perf: Add event descriptions
arm64: perf: Convert event enums to #defines
arm: perf: Add event descriptions
arm: perf: Convert event enums to #defines
drivers/perf: kill armpmu_register
This commit is contained in:
Linus Torvalds
commit
541d284be0
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@ -9,8 +9,9 @@ Required properties:
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- compatible : should be one of
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"apm,potenza-pmu"
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"arm,armv8-pmuv3"
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"arm.cortex-a57-pmu"
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"arm.cortex-a53-pmu"
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"arm,cortex-a72-pmu"
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"arm,cortex-a57-pmu"
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"arm,cortex-a53-pmu"
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"arm,cortex-a17-pmu"
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"arm,cortex-a15-pmu"
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"arm,cortex-a12-pmu"
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|
|
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@ -35,133 +35,117 @@
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* but the encodings are considered to be `reserved' in the case that
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* they are not available.
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*/
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enum armv7_perf_types {
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ARMV7_PERFCTR_PMNC_SW_INCR = 0x00,
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ARMV7_PERFCTR_L1_ICACHE_REFILL = 0x01,
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ARMV7_PERFCTR_ITLB_REFILL = 0x02,
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ARMV7_PERFCTR_L1_DCACHE_REFILL = 0x03,
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ARMV7_PERFCTR_L1_DCACHE_ACCESS = 0x04,
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ARMV7_PERFCTR_DTLB_REFILL = 0x05,
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ARMV7_PERFCTR_MEM_READ = 0x06,
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ARMV7_PERFCTR_MEM_WRITE = 0x07,
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ARMV7_PERFCTR_INSTR_EXECUTED = 0x08,
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ARMV7_PERFCTR_EXC_TAKEN = 0x09,
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ARMV7_PERFCTR_EXC_EXECUTED = 0x0A,
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ARMV7_PERFCTR_CID_WRITE = 0x0B,
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#define ARMV7_PERFCTR_PMNC_SW_INCR 0x00
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#define ARMV7_PERFCTR_L1_ICACHE_REFILL 0x01
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#define ARMV7_PERFCTR_ITLB_REFILL 0x02
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#define ARMV7_PERFCTR_L1_DCACHE_REFILL 0x03
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#define ARMV7_PERFCTR_L1_DCACHE_ACCESS 0x04
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#define ARMV7_PERFCTR_DTLB_REFILL 0x05
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#define ARMV7_PERFCTR_MEM_READ 0x06
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#define ARMV7_PERFCTR_MEM_WRITE 0x07
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#define ARMV7_PERFCTR_INSTR_EXECUTED 0x08
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#define ARMV7_PERFCTR_EXC_TAKEN 0x09
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#define ARMV7_PERFCTR_EXC_EXECUTED 0x0A
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#define ARMV7_PERFCTR_CID_WRITE 0x0B
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/*
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/*
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* ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS.
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* It counts:
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* - all (taken) branch instructions,
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* - instructions that explicitly write the PC,
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* - exception generating instructions.
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*/
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ARMV7_PERFCTR_PC_WRITE = 0x0C,
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ARMV7_PERFCTR_PC_IMM_BRANCH = 0x0D,
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ARMV7_PERFCTR_PC_PROC_RETURN = 0x0E,
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ARMV7_PERFCTR_MEM_UNALIGNED_ACCESS = 0x0F,
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ARMV7_PERFCTR_PC_BRANCH_MIS_PRED = 0x10,
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ARMV7_PERFCTR_CLOCK_CYCLES = 0x11,
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ARMV7_PERFCTR_PC_BRANCH_PRED = 0x12,
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#define ARMV7_PERFCTR_PC_WRITE 0x0C
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#define ARMV7_PERFCTR_PC_IMM_BRANCH 0x0D
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#define ARMV7_PERFCTR_PC_PROC_RETURN 0x0E
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#define ARMV7_PERFCTR_MEM_UNALIGNED_ACCESS 0x0F
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#define ARMV7_PERFCTR_PC_BRANCH_MIS_PRED 0x10
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#define ARMV7_PERFCTR_CLOCK_CYCLES 0x11
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#define ARMV7_PERFCTR_PC_BRANCH_PRED 0x12
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/* These events are defined by the PMUv2 supplement (ARM DDI 0457A). */
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ARMV7_PERFCTR_MEM_ACCESS = 0x13,
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ARMV7_PERFCTR_L1_ICACHE_ACCESS = 0x14,
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ARMV7_PERFCTR_L1_DCACHE_WB = 0x15,
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ARMV7_PERFCTR_L2_CACHE_ACCESS = 0x16,
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ARMV7_PERFCTR_L2_CACHE_REFILL = 0x17,
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ARMV7_PERFCTR_L2_CACHE_WB = 0x18,
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ARMV7_PERFCTR_BUS_ACCESS = 0x19,
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ARMV7_PERFCTR_MEM_ERROR = 0x1A,
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ARMV7_PERFCTR_INSTR_SPEC = 0x1B,
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ARMV7_PERFCTR_TTBR_WRITE = 0x1C,
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ARMV7_PERFCTR_BUS_CYCLES = 0x1D,
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/* These events are defined by the PMUv2 supplement (ARM DDI 0457A). */
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#define ARMV7_PERFCTR_MEM_ACCESS 0x13
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#define ARMV7_PERFCTR_L1_ICACHE_ACCESS 0x14
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#define ARMV7_PERFCTR_L1_DCACHE_WB 0x15
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#define ARMV7_PERFCTR_L2_CACHE_ACCESS 0x16
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#define ARMV7_PERFCTR_L2_CACHE_REFILL 0x17
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#define ARMV7_PERFCTR_L2_CACHE_WB 0x18
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#define ARMV7_PERFCTR_BUS_ACCESS 0x19
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#define ARMV7_PERFCTR_MEM_ERROR 0x1A
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#define ARMV7_PERFCTR_INSTR_SPEC 0x1B
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#define ARMV7_PERFCTR_TTBR_WRITE 0x1C
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#define ARMV7_PERFCTR_BUS_CYCLES 0x1D
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ARMV7_PERFCTR_CPU_CYCLES = 0xFF
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};
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#define ARMV7_PERFCTR_CPU_CYCLES 0xFF
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/* ARMv7 Cortex-A8 specific event types */
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enum armv7_a8_perf_types {
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ARMV7_A8_PERFCTR_L2_CACHE_ACCESS = 0x43,
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ARMV7_A8_PERFCTR_L2_CACHE_REFILL = 0x44,
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ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS = 0x50,
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ARMV7_A8_PERFCTR_STALL_ISIDE = 0x56,
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};
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#define ARMV7_A8_PERFCTR_L2_CACHE_ACCESS 0x43
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#define ARMV7_A8_PERFCTR_L2_CACHE_REFILL 0x44
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#define ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS 0x50
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#define ARMV7_A8_PERFCTR_STALL_ISIDE 0x56
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/* ARMv7 Cortex-A9 specific event types */
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enum armv7_a9_perf_types {
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ARMV7_A9_PERFCTR_INSTR_CORE_RENAME = 0x68,
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ARMV7_A9_PERFCTR_STALL_ICACHE = 0x60,
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ARMV7_A9_PERFCTR_STALL_DISPATCH = 0x66,
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};
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#define ARMV7_A9_PERFCTR_INSTR_CORE_RENAME 0x68
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#define ARMV7_A9_PERFCTR_STALL_ICACHE 0x60
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#define ARMV7_A9_PERFCTR_STALL_DISPATCH 0x66
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/* ARMv7 Cortex-A5 specific event types */
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enum armv7_a5_perf_types {
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ARMV7_A5_PERFCTR_PREFETCH_LINEFILL = 0xc2,
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ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP = 0xc3,
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};
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#define ARMV7_A5_PERFCTR_PREFETCH_LINEFILL 0xc2
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#define ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP 0xc3
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/* ARMv7 Cortex-A15 specific event types */
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enum armv7_a15_perf_types {
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ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ = 0x40,
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ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE = 0x41,
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ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ = 0x42,
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ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE = 0x43,
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#define ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ 0x40
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#define ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE 0x41
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#define ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ 0x42
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#define ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE 0x43
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ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ = 0x4C,
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ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE = 0x4D,
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#define ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ 0x4C
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#define ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE 0x4D
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ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ = 0x50,
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ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE = 0x51,
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ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ = 0x52,
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ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE = 0x53,
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#define ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ 0x50
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#define ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE 0x51
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#define ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ 0x52
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#define ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE 0x53
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ARMV7_A15_PERFCTR_PC_WRITE_SPEC = 0x76,
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};
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#define ARMV7_A15_PERFCTR_PC_WRITE_SPEC 0x76
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/* ARMv7 Cortex-A12 specific event types */
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enum armv7_a12_perf_types {
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ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_READ = 0x40,
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ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_WRITE = 0x41,
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#define ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_READ 0x40
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#define ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_WRITE 0x41
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ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_READ = 0x50,
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ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_WRITE = 0x51,
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#define ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_READ 0x50
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#define ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_WRITE 0x51
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ARMV7_A12_PERFCTR_PC_WRITE_SPEC = 0x76,
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#define ARMV7_A12_PERFCTR_PC_WRITE_SPEC 0x76
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ARMV7_A12_PERFCTR_PF_TLB_REFILL = 0xe7,
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};
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#define ARMV7_A12_PERFCTR_PF_TLB_REFILL 0xe7
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/* ARMv7 Krait specific event types */
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enum krait_perf_types {
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KRAIT_PMRESR0_GROUP0 = 0xcc,
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KRAIT_PMRESR1_GROUP0 = 0xd0,
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KRAIT_PMRESR2_GROUP0 = 0xd4,
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KRAIT_VPMRESR0_GROUP0 = 0xd8,
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#define KRAIT_PMRESR0_GROUP0 0xcc
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#define KRAIT_PMRESR1_GROUP0 0xd0
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#define KRAIT_PMRESR2_GROUP0 0xd4
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#define KRAIT_VPMRESR0_GROUP0 0xd8
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KRAIT_PERFCTR_L1_ICACHE_ACCESS = 0x10011,
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KRAIT_PERFCTR_L1_ICACHE_MISS = 0x10010,
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#define KRAIT_PERFCTR_L1_ICACHE_ACCESS 0x10011
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#define KRAIT_PERFCTR_L1_ICACHE_MISS 0x10010
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KRAIT_PERFCTR_L1_ITLB_ACCESS = 0x12222,
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KRAIT_PERFCTR_L1_DTLB_ACCESS = 0x12210,
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};
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#define KRAIT_PERFCTR_L1_ITLB_ACCESS 0x12222
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#define KRAIT_PERFCTR_L1_DTLB_ACCESS 0x12210
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/* ARMv7 Scorpion specific event types */
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enum scorpion_perf_types {
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SCORPION_LPM0_GROUP0 = 0x4c,
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SCORPION_LPM1_GROUP0 = 0x50,
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SCORPION_LPM2_GROUP0 = 0x54,
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SCORPION_L2LPM_GROUP0 = 0x58,
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SCORPION_VLPM_GROUP0 = 0x5c,
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#define SCORPION_LPM0_GROUP0 0x4c
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#define SCORPION_LPM1_GROUP0 0x50
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#define SCORPION_LPM2_GROUP0 0x54
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#define SCORPION_L2LPM_GROUP0 0x58
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#define SCORPION_VLPM_GROUP0 0x5c
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SCORPION_ICACHE_ACCESS = 0x10053,
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SCORPION_ICACHE_MISS = 0x10052,
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#define SCORPION_ICACHE_ACCESS 0x10053
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#define SCORPION_ICACHE_MISS 0x10052
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SCORPION_DTLB_ACCESS = 0x12013,
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SCORPION_DTLB_MISS = 0x12012,
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#define SCORPION_DTLB_ACCESS 0x12013
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#define SCORPION_DTLB_MISS 0x12012
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SCORPION_ITLB_MISS = 0x12021,
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};
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#define SCORPION_ITLB_MISS 0x12021
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|
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/*
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* Cortex-A8 HW events mapping
|
||||
|
|
@ -547,6 +531,134 @@ static const unsigned scorpion_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
|
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[C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
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};
|
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PMU_FORMAT_ATTR(event, "config:0-7");
|
||||
|
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static struct attribute *armv7_pmu_format_attrs[] = {
|
||||
&format_attr_event.attr,
|
||||
NULL,
|
||||
};
|
||||
|
||||
static struct attribute_group armv7_pmu_format_attr_group = {
|
||||
.name = "format",
|
||||
.attrs = armv7_pmu_format_attrs,
|
||||
};
|
||||
|
||||
#define ARMV7_EVENT_ATTR_RESOLVE(m) #m
|
||||
#define ARMV7_EVENT_ATTR(name, config) \
|
||||
PMU_EVENT_ATTR_STRING(name, armv7_event_attr_##name, \
|
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"event=" ARMV7_EVENT_ATTR_RESOLVE(config))
|
||||
|
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ARMV7_EVENT_ATTR(sw_incr, ARMV7_PERFCTR_PMNC_SW_INCR);
|
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ARMV7_EVENT_ATTR(l1i_cache_refill, ARMV7_PERFCTR_L1_ICACHE_REFILL);
|
||||
ARMV7_EVENT_ATTR(l1i_tlb_refill, ARMV7_PERFCTR_ITLB_REFILL);
|
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ARMV7_EVENT_ATTR(l1d_cache_refill, ARMV7_PERFCTR_L1_DCACHE_REFILL);
|
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ARMV7_EVENT_ATTR(l1d_cache, ARMV7_PERFCTR_L1_DCACHE_ACCESS);
|
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ARMV7_EVENT_ATTR(l1d_tlb_refill, ARMV7_PERFCTR_DTLB_REFILL);
|
||||
ARMV7_EVENT_ATTR(ld_retired, ARMV7_PERFCTR_MEM_READ);
|
||||
ARMV7_EVENT_ATTR(st_retired, ARMV7_PERFCTR_MEM_WRITE);
|
||||
ARMV7_EVENT_ATTR(inst_retired, ARMV7_PERFCTR_INSTR_EXECUTED);
|
||||
ARMV7_EVENT_ATTR(exc_taken, ARMV7_PERFCTR_EXC_TAKEN);
|
||||
ARMV7_EVENT_ATTR(exc_return, ARMV7_PERFCTR_EXC_EXECUTED);
|
||||
ARMV7_EVENT_ATTR(cid_write_retired, ARMV7_PERFCTR_CID_WRITE);
|
||||
ARMV7_EVENT_ATTR(pc_write_retired, ARMV7_PERFCTR_PC_WRITE);
|
||||
ARMV7_EVENT_ATTR(br_immed_retired, ARMV7_PERFCTR_PC_IMM_BRANCH);
|
||||
ARMV7_EVENT_ATTR(br_return_retired, ARMV7_PERFCTR_PC_PROC_RETURN);
|
||||
ARMV7_EVENT_ATTR(unaligned_ldst_retired, ARMV7_PERFCTR_MEM_UNALIGNED_ACCESS);
|
||||
ARMV7_EVENT_ATTR(br_mis_pred, ARMV7_PERFCTR_PC_BRANCH_MIS_PRED);
|
||||
ARMV7_EVENT_ATTR(cpu_cycles, ARMV7_PERFCTR_CLOCK_CYCLES);
|
||||
ARMV7_EVENT_ATTR(br_pred, ARMV7_PERFCTR_PC_BRANCH_PRED);
|
||||
|
||||
static struct attribute *armv7_pmuv1_event_attrs[] = {
|
||||
&armv7_event_attr_sw_incr.attr.attr,
|
||||
&armv7_event_attr_l1i_cache_refill.attr.attr,
|
||||
&armv7_event_attr_l1i_tlb_refill.attr.attr,
|
||||
&armv7_event_attr_l1d_cache_refill.attr.attr,
|
||||
&armv7_event_attr_l1d_cache.attr.attr,
|
||||
&armv7_event_attr_l1d_tlb_refill.attr.attr,
|
||||
&armv7_event_attr_ld_retired.attr.attr,
|
||||
&armv7_event_attr_st_retired.attr.attr,
|
||||
&armv7_event_attr_inst_retired.attr.attr,
|
||||
&armv7_event_attr_exc_taken.attr.attr,
|
||||
&armv7_event_attr_exc_return.attr.attr,
|
||||
&armv7_event_attr_cid_write_retired.attr.attr,
|
||||
&armv7_event_attr_pc_write_retired.attr.attr,
|
||||
&armv7_event_attr_br_immed_retired.attr.attr,
|
||||
&armv7_event_attr_br_return_retired.attr.attr,
|
||||
&armv7_event_attr_unaligned_ldst_retired.attr.attr,
|
||||
&armv7_event_attr_br_mis_pred.attr.attr,
|
||||
&armv7_event_attr_cpu_cycles.attr.attr,
|
||||
&armv7_event_attr_br_pred.attr.attr,
|
||||
NULL,
|
||||
};
|
||||
|
||||
static struct attribute_group armv7_pmuv1_events_attr_group = {
|
||||
.name = "events",
|
||||
.attrs = armv7_pmuv1_event_attrs,
|
||||
};
|
||||
|
||||
static const struct attribute_group *armv7_pmuv1_attr_groups[] = {
|
||||
&armv7_pmuv1_events_attr_group,
|
||||
&armv7_pmu_format_attr_group,
|
||||
NULL,
|
||||
};
|
||||
|
||||
ARMV7_EVENT_ATTR(mem_access, ARMV7_PERFCTR_MEM_ACCESS);
|
||||
ARMV7_EVENT_ATTR(l1i_cache, ARMV7_PERFCTR_L1_ICACHE_ACCESS);
|
||||
ARMV7_EVENT_ATTR(l1d_cache_wb, ARMV7_PERFCTR_L1_DCACHE_WB);
|
||||
ARMV7_EVENT_ATTR(l2d_cache, ARMV7_PERFCTR_L2_CACHE_ACCESS);
|
||||
ARMV7_EVENT_ATTR(l2d_cache_refill, ARMV7_PERFCTR_L2_CACHE_REFILL);
|
||||
ARMV7_EVENT_ATTR(l2d_cache_wb, ARMV7_PERFCTR_L2_CACHE_WB);
|
||||
ARMV7_EVENT_ATTR(bus_access, ARMV7_PERFCTR_BUS_ACCESS);
|
||||
ARMV7_EVENT_ATTR(memory_error, ARMV7_PERFCTR_MEM_ERROR);
|
||||
ARMV7_EVENT_ATTR(inst_spec, ARMV7_PERFCTR_INSTR_SPEC);
|
||||
ARMV7_EVENT_ATTR(ttbr_write_retired, ARMV7_PERFCTR_TTBR_WRITE);
|
||||
ARMV7_EVENT_ATTR(bus_cycles, ARMV7_PERFCTR_BUS_CYCLES);
|
||||
|
||||
static struct attribute *armv7_pmuv2_event_attrs[] = {
|
||||
&armv7_event_attr_sw_incr.attr.attr,
|
||||
&armv7_event_attr_l1i_cache_refill.attr.attr,
|
||||
&armv7_event_attr_l1i_tlb_refill.attr.attr,
|
||||
&armv7_event_attr_l1d_cache_refill.attr.attr,
|
||||
&armv7_event_attr_l1d_cache.attr.attr,
|
||||
&armv7_event_attr_l1d_tlb_refill.attr.attr,
|
||||
&armv7_event_attr_ld_retired.attr.attr,
|
||||
&armv7_event_attr_st_retired.attr.attr,
|
||||
&armv7_event_attr_inst_retired.attr.attr,
|
||||
&armv7_event_attr_exc_taken.attr.attr,
|
||||
&armv7_event_attr_exc_return.attr.attr,
|
||||
&armv7_event_attr_cid_write_retired.attr.attr,
|
||||
&armv7_event_attr_pc_write_retired.attr.attr,
|
||||
&armv7_event_attr_br_immed_retired.attr.attr,
|
||||
&armv7_event_attr_br_return_retired.attr.attr,
|
||||
&armv7_event_attr_unaligned_ldst_retired.attr.attr,
|
||||
&armv7_event_attr_br_mis_pred.attr.attr,
|
||||
&armv7_event_attr_cpu_cycles.attr.attr,
|
||||
&armv7_event_attr_br_pred.attr.attr,
|
||||
&armv7_event_attr_mem_access.attr.attr,
|
||||
&armv7_event_attr_l1i_cache.attr.attr,
|
||||
&armv7_event_attr_l1d_cache_wb.attr.attr,
|
||||
&armv7_event_attr_l2d_cache.attr.attr,
|
||||
&armv7_event_attr_l2d_cache_refill.attr.attr,
|
||||
&armv7_event_attr_l2d_cache_wb.attr.attr,
|
||||
&armv7_event_attr_bus_access.attr.attr,
|
||||
&armv7_event_attr_memory_error.attr.attr,
|
||||
&armv7_event_attr_inst_spec.attr.attr,
|
||||
&armv7_event_attr_ttbr_write_retired.attr.attr,
|
||||
&armv7_event_attr_bus_cycles.attr.attr,
|
||||
NULL,
|
||||
};
|
||||
|
||||
static struct attribute_group armv7_pmuv2_events_attr_group = {
|
||||
.name = "events",
|
||||
.attrs = armv7_pmuv2_event_attrs,
|
||||
};
|
||||
|
||||
static const struct attribute_group *armv7_pmuv2_attr_groups[] = {
|
||||
&armv7_pmuv2_events_attr_group,
|
||||
&armv7_pmu_format_attr_group,
|
||||
NULL,
|
||||
};
|
||||
|
||||
/*
|
||||
* Perf Events' indices
|
||||
*/
|
||||
|
|
@ -1085,6 +1197,7 @@ static int armv7_a8_pmu_init(struct arm_pmu *cpu_pmu)
|
|||
armv7pmu_init(cpu_pmu);
|
||||
cpu_pmu->name = "armv7_cortex_a8";
|
||||
cpu_pmu->map_event = armv7_a8_map_event;
|
||||
cpu_pmu->pmu.attr_groups = armv7_pmuv1_attr_groups;
|
||||
return armv7_probe_num_events(cpu_pmu);
|
||||
}
|
||||
|
||||
|
|
@ -1093,6 +1206,7 @@ static int armv7_a9_pmu_init(struct arm_pmu *cpu_pmu)
|
|||
armv7pmu_init(cpu_pmu);
|
||||
cpu_pmu->name = "armv7_cortex_a9";
|
||||
cpu_pmu->map_event = armv7_a9_map_event;
|
||||
cpu_pmu->pmu.attr_groups = armv7_pmuv1_attr_groups;
|
||||
return armv7_probe_num_events(cpu_pmu);
|
||||
}
|
||||
|
||||
|
|
@ -1101,6 +1215,7 @@ static int armv7_a5_pmu_init(struct arm_pmu *cpu_pmu)
|
|||
armv7pmu_init(cpu_pmu);
|
||||
cpu_pmu->name = "armv7_cortex_a5";
|
||||
cpu_pmu->map_event = armv7_a5_map_event;
|
||||
cpu_pmu->pmu.attr_groups = armv7_pmuv1_attr_groups;
|
||||
return armv7_probe_num_events(cpu_pmu);
|
||||
}
|
||||
|
||||
|
|
@ -1110,6 +1225,7 @@ static int armv7_a15_pmu_init(struct arm_pmu *cpu_pmu)
|
|||
cpu_pmu->name = "armv7_cortex_a15";
|
||||
cpu_pmu->map_event = armv7_a15_map_event;
|
||||
cpu_pmu->set_event_filter = armv7pmu_set_event_filter;
|
||||
cpu_pmu->pmu.attr_groups = armv7_pmuv2_attr_groups;
|
||||
return armv7_probe_num_events(cpu_pmu);
|
||||
}
|
||||
|
||||
|
|
@ -1119,6 +1235,7 @@ static int armv7_a7_pmu_init(struct arm_pmu *cpu_pmu)
|
|||
cpu_pmu->name = "armv7_cortex_a7";
|
||||
cpu_pmu->map_event = armv7_a7_map_event;
|
||||
cpu_pmu->set_event_filter = armv7pmu_set_event_filter;
|
||||
cpu_pmu->pmu.attr_groups = armv7_pmuv2_attr_groups;
|
||||
return armv7_probe_num_events(cpu_pmu);
|
||||
}
|
||||
|
||||
|
|
@ -1128,6 +1245,7 @@ static int armv7_a12_pmu_init(struct arm_pmu *cpu_pmu)
|
|||
cpu_pmu->name = "armv7_cortex_a12";
|
||||
cpu_pmu->map_event = armv7_a12_map_event;
|
||||
cpu_pmu->set_event_filter = armv7pmu_set_event_filter;
|
||||
cpu_pmu->pmu.attr_groups = armv7_pmuv2_attr_groups;
|
||||
return armv7_probe_num_events(cpu_pmu);
|
||||
}
|
||||
|
||||
|
|
@ -1135,6 +1253,7 @@ static int armv7_a17_pmu_init(struct arm_pmu *cpu_pmu)
|
|||
{
|
||||
int ret = armv7_a12_pmu_init(cpu_pmu);
|
||||
cpu_pmu->name = "armv7_cortex_a17";
|
||||
cpu_pmu->pmu.attr_groups = armv7_pmuv2_attr_groups;
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -29,60 +29,74 @@
|
|||
* ARMv8 PMUv3 Performance Events handling code.
|
||||
* Common event types.
|
||||
*/
|
||||
enum armv8_pmuv3_perf_types {
|
||||
/* Required events. */
|
||||
ARMV8_PMUV3_PERFCTR_PMNC_SW_INCR = 0x00,
|
||||
ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL = 0x03,
|
||||
ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS = 0x04,
|
||||
ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED = 0x10,
|
||||
ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES = 0x11,
|
||||
ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED = 0x12,
|
||||
|
||||
/* At least one of the following is required. */
|
||||
ARMV8_PMUV3_PERFCTR_INSTR_EXECUTED = 0x08,
|
||||
ARMV8_PMUV3_PERFCTR_OP_SPEC = 0x1B,
|
||||
/* Required events. */
|
||||
#define ARMV8_PMUV3_PERFCTR_PMNC_SW_INCR 0x00
|
||||
#define ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL 0x03
|
||||
#define ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS 0x04
|
||||
#define ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED 0x10
|
||||
#define ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES 0x11
|
||||
#define ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED 0x12
|
||||
|
||||
/* Common architectural events. */
|
||||
ARMV8_PMUV3_PERFCTR_MEM_READ = 0x06,
|
||||
ARMV8_PMUV3_PERFCTR_MEM_WRITE = 0x07,
|
||||
ARMV8_PMUV3_PERFCTR_EXC_TAKEN = 0x09,
|
||||
ARMV8_PMUV3_PERFCTR_EXC_EXECUTED = 0x0A,
|
||||
ARMV8_PMUV3_PERFCTR_CID_WRITE = 0x0B,
|
||||
ARMV8_PMUV3_PERFCTR_PC_WRITE = 0x0C,
|
||||
ARMV8_PMUV3_PERFCTR_PC_IMM_BRANCH = 0x0D,
|
||||
ARMV8_PMUV3_PERFCTR_PC_PROC_RETURN = 0x0E,
|
||||
ARMV8_PMUV3_PERFCTR_MEM_UNALIGNED_ACCESS = 0x0F,
|
||||
ARMV8_PMUV3_PERFCTR_TTBR_WRITE = 0x1C,
|
||||
/* At least one of the following is required. */
|
||||
#define ARMV8_PMUV3_PERFCTR_INSTR_EXECUTED 0x08
|
||||
#define ARMV8_PMUV3_PERFCTR_OP_SPEC 0x1B
|
||||
|
||||
/* Common microarchitectural events. */
|
||||
ARMV8_PMUV3_PERFCTR_L1_ICACHE_REFILL = 0x01,
|
||||
ARMV8_PMUV3_PERFCTR_ITLB_REFILL = 0x02,
|
||||
ARMV8_PMUV3_PERFCTR_DTLB_REFILL = 0x05,
|
||||
ARMV8_PMUV3_PERFCTR_MEM_ACCESS = 0x13,
|
||||
ARMV8_PMUV3_PERFCTR_L1_ICACHE_ACCESS = 0x14,
|
||||
ARMV8_PMUV3_PERFCTR_L1_DCACHE_WB = 0x15,
|
||||
ARMV8_PMUV3_PERFCTR_L2_CACHE_ACCESS = 0x16,
|
||||
ARMV8_PMUV3_PERFCTR_L2_CACHE_REFILL = 0x17,
|
||||
ARMV8_PMUV3_PERFCTR_L2_CACHE_WB = 0x18,
|
||||
ARMV8_PMUV3_PERFCTR_BUS_ACCESS = 0x19,
|
||||
ARMV8_PMUV3_PERFCTR_MEM_ERROR = 0x1A,
|
||||
ARMV8_PMUV3_PERFCTR_BUS_CYCLES = 0x1D,
|
||||
};
|
||||
/* Common architectural events. */
|
||||
#define ARMV8_PMUV3_PERFCTR_MEM_READ 0x06
|
||||
#define ARMV8_PMUV3_PERFCTR_MEM_WRITE 0x07
|
||||
#define ARMV8_PMUV3_PERFCTR_EXC_TAKEN 0x09
|
||||
#define ARMV8_PMUV3_PERFCTR_EXC_EXECUTED 0x0A
|
||||
#define ARMV8_PMUV3_PERFCTR_CID_WRITE 0x0B
|
||||
#define ARMV8_PMUV3_PERFCTR_PC_WRITE 0x0C
|
||||
#define ARMV8_PMUV3_PERFCTR_PC_IMM_BRANCH 0x0D
|
||||
#define ARMV8_PMUV3_PERFCTR_PC_PROC_RETURN 0x0E
|
||||
#define ARMV8_PMUV3_PERFCTR_MEM_UNALIGNED_ACCESS 0x0F
|
||||
#define ARMV8_PMUV3_PERFCTR_TTBR_WRITE 0x1C
|
||||
#define ARMV8_PMUV3_PERFCTR_CHAIN 0x1E
|
||||
#define ARMV8_PMUV3_PERFCTR_BR_RETIRED 0x21
|
||||
|
||||
/* Common microarchitectural events. */
|
||||
#define ARMV8_PMUV3_PERFCTR_L1_ICACHE_REFILL 0x01
|
||||
#define ARMV8_PMUV3_PERFCTR_ITLB_REFILL 0x02
|
||||
#define ARMV8_PMUV3_PERFCTR_DTLB_REFILL 0x05
|
||||
#define ARMV8_PMUV3_PERFCTR_MEM_ACCESS 0x13
|
||||
#define ARMV8_PMUV3_PERFCTR_L1_ICACHE_ACCESS 0x14
|
||||
#define ARMV8_PMUV3_PERFCTR_L1_DCACHE_WB 0x15
|
||||
#define ARMV8_PMUV3_PERFCTR_L2_CACHE_ACCESS 0x16
|
||||
#define ARMV8_PMUV3_PERFCTR_L2_CACHE_REFILL 0x17
|
||||
#define ARMV8_PMUV3_PERFCTR_L2_CACHE_WB 0x18
|
||||
#define ARMV8_PMUV3_PERFCTR_BUS_ACCESS 0x19
|
||||
#define ARMV8_PMUV3_PERFCTR_MEM_ERROR 0x1A
|
||||
#define ARMV8_PMUV3_PERFCTR_BUS_CYCLES 0x1D
|
||||
#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE 0x1F
|
||||
#define ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE 0x20
|
||||
#define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED 0x22
|
||||
#define ARMV8_PMUV3_PERFCTR_STALL_FRONTEND 0x23
|
||||
#define ARMV8_PMUV3_PERFCTR_STALL_BACKEND 0x24
|
||||
#define ARMV8_PMUV3_PERFCTR_L1D_TLB 0x25
|
||||
#define ARMV8_PMUV3_PERFCTR_L1I_TLB 0x26
|
||||
#define ARMV8_PMUV3_PERFCTR_L2I_CACHE 0x27
|
||||
#define ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL 0x28
|
||||
#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE 0x29
|
||||
#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL 0x2A
|
||||
#define ARMV8_PMUV3_PERFCTR_L3D_CACHE 0x2B
|
||||
#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB 0x2C
|
||||
#define ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL 0x2D
|
||||
#define ARMV8_PMUV3_PERFCTR_L21_TLB_REFILL 0x2E
|
||||
#define ARMV8_PMUV3_PERFCTR_L2D_TLB 0x2F
|
||||
#define ARMV8_PMUV3_PERFCTR_L21_TLB 0x30
|
||||
|
||||
/* ARMv8 Cortex-A53 specific event types. */
|
||||
enum armv8_a53_pmu_perf_types {
|
||||
ARMV8_A53_PERFCTR_PREFETCH_LINEFILL = 0xC2,
|
||||
};
|
||||
#define ARMV8_A53_PERFCTR_PREFETCH_LINEFILL 0xC2
|
||||
|
||||
/* ARMv8 Cortex-A57 specific event types. */
|
||||
enum armv8_a57_perf_types {
|
||||
ARMV8_A57_PERFCTR_L1_DCACHE_ACCESS_LD = 0x40,
|
||||
ARMV8_A57_PERFCTR_L1_DCACHE_ACCESS_ST = 0x41,
|
||||
ARMV8_A57_PERFCTR_L1_DCACHE_REFILL_LD = 0x42,
|
||||
ARMV8_A57_PERFCTR_L1_DCACHE_REFILL_ST = 0x43,
|
||||
ARMV8_A57_PERFCTR_DTLB_REFILL_LD = 0x4c,
|
||||
ARMV8_A57_PERFCTR_DTLB_REFILL_ST = 0x4d,
|
||||
};
|
||||
/* ARMv8 Cortex-A57 and Cortex-A72 specific event types. */
|
||||
#define ARMV8_A57_PERFCTR_L1_DCACHE_ACCESS_LD 0x40
|
||||
#define ARMV8_A57_PERFCTR_L1_DCACHE_ACCESS_ST 0x41
|
||||
#define ARMV8_A57_PERFCTR_L1_DCACHE_REFILL_LD 0x42
|
||||
#define ARMV8_A57_PERFCTR_L1_DCACHE_REFILL_ST 0x43
|
||||
#define ARMV8_A57_PERFCTR_DTLB_REFILL_LD 0x4c
|
||||
#define ARMV8_A57_PERFCTR_DTLB_REFILL_ST 0x4d
|
||||
|
||||
/* PMUv3 HW events mapping. */
|
||||
static const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX] = {
|
||||
|
|
@ -106,6 +120,7 @@ static const unsigned armv8_a53_perf_map[PERF_COUNT_HW_MAX] = {
|
|||
[PERF_COUNT_HW_BUS_CYCLES] = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
|
||||
};
|
||||
|
||||
/* ARM Cortex-A57 and Cortex-A72 events mapping. */
|
||||
static const unsigned armv8_a57_perf_map[PERF_COUNT_HW_MAX] = {
|
||||
PERF_MAP_ALL_UNSUPPORTED,
|
||||
[PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES,
|
||||
|
|
@ -178,6 +193,137 @@ static const unsigned armv8_a57_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
|
|||
[C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
|
||||
};
|
||||
|
||||
#define ARMV8_EVENT_ATTR_RESOLVE(m) #m
|
||||
#define ARMV8_EVENT_ATTR(name, config) \
|
||||
PMU_EVENT_ATTR_STRING(name, armv8_event_attr_##name, \
|
||||
"event=" ARMV8_EVENT_ATTR_RESOLVE(config))
|
||||
|
||||
ARMV8_EVENT_ATTR(sw_incr, ARMV8_PMUV3_PERFCTR_PMNC_SW_INCR);
|
||||
ARMV8_EVENT_ATTR(l1i_cache_refill, ARMV8_PMUV3_PERFCTR_L1_ICACHE_REFILL);
|
||||
ARMV8_EVENT_ATTR(l1i_tlb_refill, ARMV8_PMUV3_PERFCTR_ITLB_REFILL);
|
||||
ARMV8_EVENT_ATTR(l1d_cache_refill, ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL);
|
||||
ARMV8_EVENT_ATTR(l1d_cache, ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS);
|
||||
ARMV8_EVENT_ATTR(l1d_tlb_refill, ARMV8_PMUV3_PERFCTR_DTLB_REFILL);
|
||||
ARMV8_EVENT_ATTR(ld_retired, ARMV8_PMUV3_PERFCTR_MEM_READ);
|
||||
ARMV8_EVENT_ATTR(st_retired, ARMV8_PMUV3_PERFCTR_MEM_WRITE);
|
||||
ARMV8_EVENT_ATTR(inst_retired, ARMV8_PMUV3_PERFCTR_INSTR_EXECUTED);
|
||||
ARMV8_EVENT_ATTR(exc_taken, ARMV8_PMUV3_PERFCTR_EXC_TAKEN);
|
||||
ARMV8_EVENT_ATTR(exc_return, ARMV8_PMUV3_PERFCTR_EXC_EXECUTED);
|
||||
ARMV8_EVENT_ATTR(cid_write_retired, ARMV8_PMUV3_PERFCTR_CID_WRITE);
|
||||
ARMV8_EVENT_ATTR(pc_write_retired, ARMV8_PMUV3_PERFCTR_PC_WRITE);
|
||||
ARMV8_EVENT_ATTR(br_immed_retired, ARMV8_PMUV3_PERFCTR_PC_IMM_BRANCH);
|
||||
ARMV8_EVENT_ATTR(br_return_retired, ARMV8_PMUV3_PERFCTR_PC_PROC_RETURN);
|
||||
ARMV8_EVENT_ATTR(unaligned_ldst_retired, ARMV8_PMUV3_PERFCTR_MEM_UNALIGNED_ACCESS);
|
||||
ARMV8_EVENT_ATTR(br_mis_pred, ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED);
|
||||
ARMV8_EVENT_ATTR(cpu_cycles, ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES);
|
||||
ARMV8_EVENT_ATTR(br_pred, ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED);
|
||||
ARMV8_EVENT_ATTR(mem_access, ARMV8_PMUV3_PERFCTR_MEM_ACCESS);
|
||||
ARMV8_EVENT_ATTR(l1i_cache, ARMV8_PMUV3_PERFCTR_L1_ICACHE_ACCESS);
|
||||
ARMV8_EVENT_ATTR(l1d_cache_wb, ARMV8_PMUV3_PERFCTR_L1_DCACHE_WB);
|
||||
ARMV8_EVENT_ATTR(l2d_cache, ARMV8_PMUV3_PERFCTR_L2_CACHE_ACCESS);
|
||||
ARMV8_EVENT_ATTR(l2d_cache_refill, ARMV8_PMUV3_PERFCTR_L2_CACHE_REFILL);
|
||||
ARMV8_EVENT_ATTR(l2d_cache_wb, ARMV8_PMUV3_PERFCTR_L2_CACHE_WB);
|
||||
ARMV8_EVENT_ATTR(bus_access, ARMV8_PMUV3_PERFCTR_BUS_ACCESS);
|
||||
ARMV8_EVENT_ATTR(memory_error, ARMV8_PMUV3_PERFCTR_MEM_ERROR);
|
||||
ARMV8_EVENT_ATTR(inst_spec, ARMV8_PMUV3_PERFCTR_OP_SPEC);
|
||||
ARMV8_EVENT_ATTR(ttbr_write_retired, ARMV8_PMUV3_PERFCTR_TTBR_WRITE);
|
||||
ARMV8_EVENT_ATTR(bus_cycles, ARMV8_PMUV3_PERFCTR_BUS_CYCLES);
|
||||
ARMV8_EVENT_ATTR(chain, ARMV8_PMUV3_PERFCTR_CHAIN);
|
||||
ARMV8_EVENT_ATTR(l1d_cache_allocate, ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE);
|
||||
ARMV8_EVENT_ATTR(l2d_cache_allocate, ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE);
|
||||
ARMV8_EVENT_ATTR(br_retired, ARMV8_PMUV3_PERFCTR_BR_RETIRED);
|
||||
ARMV8_EVENT_ATTR(br_mis_pred_retired, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED);
|
||||
ARMV8_EVENT_ATTR(stall_frontend, ARMV8_PMUV3_PERFCTR_STALL_FRONTEND);
|
||||
ARMV8_EVENT_ATTR(stall_backend, ARMV8_PMUV3_PERFCTR_STALL_BACKEND);
|
||||
ARMV8_EVENT_ATTR(l1d_tlb, ARMV8_PMUV3_PERFCTR_L1D_TLB);
|
||||
ARMV8_EVENT_ATTR(l1i_tlb, ARMV8_PMUV3_PERFCTR_L1I_TLB);
|
||||
ARMV8_EVENT_ATTR(l2i_cache, ARMV8_PMUV3_PERFCTR_L2I_CACHE);
|
||||
ARMV8_EVENT_ATTR(l2i_cache_refill, ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL);
|
||||
ARMV8_EVENT_ATTR(l3d_cache_allocate, ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE);
|
||||
ARMV8_EVENT_ATTR(l3d_cache_refill, ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL);
|
||||
ARMV8_EVENT_ATTR(l3d_cache, ARMV8_PMUV3_PERFCTR_L3D_CACHE);
|
||||
ARMV8_EVENT_ATTR(l3d_cache_wb, ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB);
|
||||
ARMV8_EVENT_ATTR(l2d_tlb_refill, ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL);
|
||||
ARMV8_EVENT_ATTR(l21_tlb_refill, ARMV8_PMUV3_PERFCTR_L21_TLB_REFILL);
|
||||
ARMV8_EVENT_ATTR(l2d_tlb, ARMV8_PMUV3_PERFCTR_L2D_TLB);
|
||||
ARMV8_EVENT_ATTR(l21_tlb, ARMV8_PMUV3_PERFCTR_L21_TLB);
|
||||
|
||||
static struct attribute *armv8_pmuv3_event_attrs[] = {
|
||||
&armv8_event_attr_sw_incr.attr.attr,
|
||||
&armv8_event_attr_l1i_cache_refill.attr.attr,
|
||||
&armv8_event_attr_l1i_tlb_refill.attr.attr,
|
||||
&armv8_event_attr_l1d_cache_refill.attr.attr,
|
||||
&armv8_event_attr_l1d_cache.attr.attr,
|
||||
&armv8_event_attr_l1d_tlb_refill.attr.attr,
|
||||
&armv8_event_attr_ld_retired.attr.attr,
|
||||
&armv8_event_attr_st_retired.attr.attr,
|
||||
&armv8_event_attr_inst_retired.attr.attr,
|
||||
&armv8_event_attr_exc_taken.attr.attr,
|
||||
&armv8_event_attr_exc_return.attr.attr,
|
||||
&armv8_event_attr_cid_write_retired.attr.attr,
|
||||
&armv8_event_attr_pc_write_retired.attr.attr,
|
||||
&armv8_event_attr_br_immed_retired.attr.attr,
|
||||
&armv8_event_attr_br_return_retired.attr.attr,
|
||||
&armv8_event_attr_unaligned_ldst_retired.attr.attr,
|
||||
&armv8_event_attr_br_mis_pred.attr.attr,
|
||||
&armv8_event_attr_cpu_cycles.attr.attr,
|
||||
&armv8_event_attr_br_pred.attr.attr,
|
||||
&armv8_event_attr_mem_access.attr.attr,
|
||||
&armv8_event_attr_l1i_cache.attr.attr,
|
||||
&armv8_event_attr_l1d_cache_wb.attr.attr,
|
||||
&armv8_event_attr_l2d_cache.attr.attr,
|
||||
&armv8_event_attr_l2d_cache_refill.attr.attr,
|
||||
&armv8_event_attr_l2d_cache_wb.attr.attr,
|
||||
&armv8_event_attr_bus_access.attr.attr,
|
||||
&armv8_event_attr_memory_error.attr.attr,
|
||||
&armv8_event_attr_inst_spec.attr.attr,
|
||||
&armv8_event_attr_ttbr_write_retired.attr.attr,
|
||||
&armv8_event_attr_bus_cycles.attr.attr,
|
||||
&armv8_event_attr_chain.attr.attr,
|
||||
&armv8_event_attr_l1d_cache_allocate.attr.attr,
|
||||
&armv8_event_attr_l2d_cache_allocate.attr.attr,
|
||||
&armv8_event_attr_br_retired.attr.attr,
|
||||
&armv8_event_attr_br_mis_pred_retired.attr.attr,
|
||||
&armv8_event_attr_stall_frontend.attr.attr,
|
||||
&armv8_event_attr_stall_backend.attr.attr,
|
||||
&armv8_event_attr_l1d_tlb.attr.attr,
|
||||
&armv8_event_attr_l1i_tlb.attr.attr,
|
||||
&armv8_event_attr_l2i_cache.attr.attr,
|
||||
&armv8_event_attr_l2i_cache_refill.attr.attr,
|
||||
&armv8_event_attr_l3d_cache_allocate.attr.attr,
|
||||
&armv8_event_attr_l3d_cache_refill.attr.attr,
|
||||
&armv8_event_attr_l3d_cache.attr.attr,
|
||||
&armv8_event_attr_l3d_cache_wb.attr.attr,
|
||||
&armv8_event_attr_l2d_tlb_refill.attr.attr,
|
||||
&armv8_event_attr_l21_tlb_refill.attr.attr,
|
||||
&armv8_event_attr_l2d_tlb.attr.attr,
|
||||
&armv8_event_attr_l21_tlb.attr.attr,
|
||||
NULL,
|
||||
};
|
||||
|
||||
static struct attribute_group armv8_pmuv3_events_attr_group = {
|
||||
.name = "events",
|
||||
.attrs = armv8_pmuv3_event_attrs,
|
||||
};
|
||||
|
||||
PMU_FORMAT_ATTR(event, "config:0-9");
|
||||
|
||||
static struct attribute *armv8_pmuv3_format_attrs[] = {
|
||||
&format_attr_event.attr,
|
||||
NULL,
|
||||
};
|
||||
|
||||
static struct attribute_group armv8_pmuv3_format_attr_group = {
|
||||
.name = "format",
|
||||
.attrs = armv8_pmuv3_format_attrs,
|
||||
};
|
||||
|
||||
static const struct attribute_group *armv8_pmuv3_attr_groups[] = {
|
||||
&armv8_pmuv3_events_attr_group,
|
||||
&armv8_pmuv3_format_attr_group,
|
||||
NULL,
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* Perf Events' indices
|
||||
|
|
@ -574,9 +720,6 @@ static void armv8pmu_reset(void *info)
|
|||
|
||||
/* Initialize & Reset PMNC: C and P bits. */
|
||||
armv8pmu_pmcr_write(ARMV8_PMCR_P | ARMV8_PMCR_C);
|
||||
|
||||
/* Disable access from userspace. */
|
||||
asm volatile("msr pmuserenr_el0, %0" :: "r" (0));
|
||||
}
|
||||
|
||||
static int armv8_pmuv3_map_event(struct perf_event *event)
|
||||
|
|
@ -646,6 +789,7 @@ static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu)
|
|||
armv8_pmu_init(cpu_pmu);
|
||||
cpu_pmu->name = "armv8_cortex_a53";
|
||||
cpu_pmu->map_event = armv8_a53_map_event;
|
||||
cpu_pmu->pmu.attr_groups = armv8_pmuv3_attr_groups;
|
||||
return armv8pmu_probe_num_events(cpu_pmu);
|
||||
}
|
||||
|
||||
|
|
@ -654,6 +798,16 @@ static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)
|
|||
armv8_pmu_init(cpu_pmu);
|
||||
cpu_pmu->name = "armv8_cortex_a57";
|
||||
cpu_pmu->map_event = armv8_a57_map_event;
|
||||
cpu_pmu->pmu.attr_groups = armv8_pmuv3_attr_groups;
|
||||
return armv8pmu_probe_num_events(cpu_pmu);
|
||||
}
|
||||
|
||||
static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu)
|
||||
{
|
||||
armv8_pmu_init(cpu_pmu);
|
||||
cpu_pmu->name = "armv8_cortex_a72";
|
||||
cpu_pmu->map_event = armv8_a57_map_event;
|
||||
cpu_pmu->pmu.attr_groups = armv8_pmuv3_attr_groups;
|
||||
return armv8pmu_probe_num_events(cpu_pmu);
|
||||
}
|
||||
|
||||
|
|
@ -661,6 +815,7 @@ static const struct of_device_id armv8_pmu_of_device_ids[] = {
|
|||
{.compatible = "arm,armv8-pmuv3", .data = armv8_pmuv3_init},
|
||||
{.compatible = "arm,cortex-a53-pmu", .data = armv8_a53_pmu_init},
|
||||
{.compatible = "arm,cortex-a57-pmu", .data = armv8_a57_pmu_init},
|
||||
{.compatible = "arm,cortex-a72-pmu", .data = armv8_a72_pmu_init},
|
||||
{},
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -117,6 +117,7 @@ ENTRY(cpu_do_resume)
|
|||
*/
|
||||
ubfx x11, x11, #1, #1
|
||||
msr oslar_el1, x11
|
||||
msr pmuserenr_el0, xzr // Disable PMU access from EL0
|
||||
mov x0, x12
|
||||
dsb nsh // Make sure local tlb invalidation completed
|
||||
isb
|
||||
|
|
@ -153,6 +154,7 @@ ENTRY(__cpu_setup)
|
|||
msr cpacr_el1, x0 // Enable FP/ASIMD
|
||||
mov x0, #1 << 12 // Reset mdscr_el1 and disable
|
||||
msr mdscr_el1, x0 // access to the DCC from EL0
|
||||
msr pmuserenr_el0, xzr // Disable PMU access from EL0
|
||||
/*
|
||||
* Memory region attributes for LPAE:
|
||||
*
|
||||
|
|
|
|||
|
|
@ -551,14 +551,6 @@ static void armpmu_init(struct arm_pmu *armpmu)
|
|||
};
|
||||
}
|
||||
|
||||
int armpmu_register(struct arm_pmu *armpmu, int type)
|
||||
{
|
||||
armpmu_init(armpmu);
|
||||
pr_info("enabled with %s PMU driver, %d counters available\n",
|
||||
armpmu->name, armpmu->num_events);
|
||||
return perf_pmu_register(&armpmu->pmu, armpmu->name, type);
|
||||
}
|
||||
|
||||
/* Set at runtime when we know what CPU type we are. */
|
||||
static struct arm_pmu *__oprofile_cpu_pmu;
|
||||
|
||||
|
|
@ -887,6 +879,8 @@ int arm_pmu_device_probe(struct platform_device *pdev,
|
|||
return -ENOMEM;
|
||||
}
|
||||
|
||||
armpmu_init(pmu);
|
||||
|
||||
if (!__oprofile_cpu_pmu)
|
||||
__oprofile_cpu_pmu = pmu;
|
||||
|
||||
|
|
@ -912,10 +906,13 @@ int arm_pmu_device_probe(struct platform_device *pdev,
|
|||
if (ret)
|
||||
goto out_free;
|
||||
|
||||
ret = armpmu_register(pmu, -1);
|
||||
ret = perf_pmu_register(&pmu->pmu, pmu->name, -1);
|
||||
if (ret)
|
||||
goto out_destroy;
|
||||
|
||||
pr_info("enabled with %s PMU driver, %d counters available\n",
|
||||
pmu->name, pmu->num_events);
|
||||
|
||||
return 0;
|
||||
|
||||
out_destroy:
|
||||
|
|
|
|||
|
|
@ -111,8 +111,6 @@ struct arm_pmu {
|
|||
|
||||
#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
|
||||
|
||||
int armpmu_register(struct arm_pmu *armpmu, int type);
|
||||
|
||||
u64 armpmu_event_update(struct perf_event *event);
|
||||
|
||||
int armpmu_event_set_period(struct perf_event *event);
|
||||
|
|
|
|||
Loading…
Reference in New Issue