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Samsung mach/soc update for v4.8, part 2: 

1. Endian-friendly fixes.
 2. Maintainers update.
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Merge tag 'samsung-soc-4.8-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/soc

Samsung mach/soc update for v4.8, part 2:
1. Endian-friendly fixes.
2. Maintainers update.

* tag 'samsung-soc-4.8-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  MAINTAINERS: Extend Samsung SoC entry with S3C/S5P drivers
  ARM: SAMSUNG: Fix missing s5p_init_cpu() declaration
  ARM: EXYNOS: Fix UART address selection for DEBUG_LL
  ARM: EXYNOS: Fixup for __raw operations in suspend.c
  ARM: SAMSUNG: Fixup usage of __raw IO in PM
  ARM: EXYNOS: Fixup endian in pm/pmu
  ARM: EXYNOS: Fixups for big-endian operation
  ARM: SAMSUNG: Fixup endian issues in CPU detection
  ARM: EXYNOS: Fixup debug macros for big-endian
  ARM: s3c24xx: Sort cpufreq tables
  ARM: SAMSUNG: Fix typos

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2016-07-05 22:41:01 -07:00
parent df92d2e393 1c03274d68
commit 553228d073
27 changed files with 69 additions and 48 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
MAINTAINERS
View File

@ -1598,8 +1598,10 @@ F: arch/arm/mach-s3c24*/
F: arch/arm/mach-s3c64xx/
F: arch/arm/mach-s5p*/
F: arch/arm/mach-exynos*/
F: drivers/*/*s3c2410*
F: drivers/*/*/*s3c2410*
F: drivers/*/*s3c24*
F: drivers/*/*/*s3c24*
F: drivers/*/*s3c64xx*
F: drivers/*/*s5pv210*
F: drivers/memory/samsung/*
F: drivers/soc/samsung/*
F: drivers/spi/spi-s3c*

6
arch/arm/include/debug/exynos.S
View File

@ -24,7 +24,11 @@
mrc p15, 0, \tmp, c0, c0, 0
and \tmp, \tmp, #0xf0
teq \tmp, #0xf0 @@ A15
ldreq \rp, =EXYNOS5_PA_UART
beq 100f
mrc p15, 0, \tmp, c0, c0, 5
and \tmp, \tmp, #0xf00
teq \tmp, #0x100 @@ A15 + A7 but boot to A7
100: ldreq \rp, =EXYNOS5_PA_UART
movne \rp, #EXYNOS4_PA_UART @@ EXYNOS4
ldr \rv, =S3C_VA_UART
#if CONFIG_DEBUG_S3C_UART != 0

8
arch/arm/include/debug/samsung.S
View File

@ -15,11 +15,13 @@
.macro fifo_level_s5pv210 rd, rx
ldr \rd, [\rx, # S3C2410_UFSTAT]
ARM_BE8(rev \rd, \rd)
and \rd, \rd, #S5PV210_UFSTAT_TXMASK
.endm
.macro fifo_full_s5pv210 rd, rx
ldr \rd, [\rx, # S3C2410_UFSTAT]
ARM_BE8(rev \rd, \rd)
tst \rd, #S5PV210_UFSTAT_TXFULL
.endm
@ -28,6 +30,7 @@
.macro fifo_level_s3c2440 rd, rx
ldr \rd, [\rx, # S3C2410_UFSTAT]
ARM_BE8(rev \rd, \rd)
and \rd, \rd, #S3C2440_UFSTAT_TXMASK
.endm
@ -37,6 +40,7 @@
.macro fifo_full_s3c2440 rd, rx
ldr \rd, [\rx, # S3C2410_UFSTAT]
ARM_BE8(rev \rd, \rd)
tst \rd, #S3C2440_UFSTAT_TXFULL
.endm
@ -50,6 +54,7 @@
.macro busyuart, rd, rx
ldr \rd, [\rx, # S3C2410_UFCON]
ARM_BE8(rev \rd, \rd)
tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled?
beq 1001f @
@ FIFO enabled...
@ -61,6 +66,7 @@
1001:
@ busy waiting for non fifo
ldr \rd, [\rx, # S3C2410_UTRSTAT]
ARM_BE8(rev \rd, \rd)
tst \rd, #S3C2410_UTRSTAT_TXFE
beq 1001b
@ -69,6 +75,7 @@
.macro waituart,rd,rx
ldr \rd, [\rx, # S3C2410_UFCON]
ARM_BE8(rev \rd, \rd)
tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled?
beq 1001f @
@ FIFO enabled...
@ -80,6 +87,7 @@
1001:
@ idle waiting for non fifo
ldr \rd, [\rx, # S3C2410_UTRSTAT]
ARM_BE8(rev \rd, \rd)
tst \rd, #S3C2410_UTRSTAT_TXFE
beq 1001b

5
arch/arm/mach-exynos/common.h
View File

@ -166,7 +166,6 @@ extern struct cpuidle_exynos_data cpuidle_coupled_exynos_data;
extern void exynos_set_delayed_reset_assertion(bool enable);
extern void s5p_init_cpu(void __iomem *cpuid_addr);
extern unsigned int samsung_rev(void);
extern void exynos_core_restart(u32 core_id);
extern int exynos_set_boot_addr(u32 core_id, unsigned long boot_addr);
@ -174,12 +173,12 @@ extern int exynos_get_boot_addr(u32 core_id, unsigned long *boot_addr);
static inline void pmu_raw_writel(u32 val, u32 offset)
{
__raw_writel(val, pmu_base_addr + offset);
writel_relaxed(val, pmu_base_addr + offset);
}
static inline u32 pmu_raw_readl(u32 offset)
{
return __raw_readl(pmu_base_addr + offset);
return readl_relaxed(pmu_base_addr + offset);
}
#endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */

1
arch/arm/mach-exynos/exynos.c
View File

@ -25,6 +25,7 @@
#include <asm/mach/map.h>
#include <mach/map.h>
#include <plat/cpu.h>
#include "common.h"
#include "mfc.h"

18
arch/arm/mach-exynos/firmware.c
View File

@ -41,9 +41,9 @@ static int exynos_do_idle(unsigned long mode)
case FW_DO_IDLE_AFTR:
if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
exynos_save_cp15();
__raw_writel(virt_to_phys(exynos_cpu_resume_ns),
sysram_ns_base_addr + 0x24);
__raw_writel(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20);
writel_relaxed(virt_to_phys(exynos_cpu_resume_ns),
sysram_ns_base_addr + 0x24);
writel_relaxed(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20);
if (soc_is_exynos3250()) {
flush_cache_all();
exynos_smc(SMC_CMD_SAVE, OP_TYPE_CORE,
@ -97,7 +97,7 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
if (soc_is_exynos4412())
boot_reg += 4 * cpu;
__raw_writel(boot_addr, boot_reg);
writel_relaxed(boot_addr, boot_reg);
return 0;
}
@ -113,7 +113,7 @@ static int exynos_get_cpu_boot_addr(int cpu, unsigned long *boot_addr)
if (soc_is_exynos4412())
boot_reg += 4 * cpu;
*boot_addr = __raw_readl(boot_reg);
*boot_addr = readl_relaxed(boot_reg);
return 0;
}
@ -234,20 +234,20 @@ void exynos_set_boot_flag(unsigned int cpu, unsigned int mode)
{
unsigned int tmp;
tmp = __raw_readl(REG_CPU_STATE_ADDR + cpu * 4);
tmp = readl_relaxed(REG_CPU_STATE_ADDR + cpu * 4);
if (mode & BOOT_MODE_MASK)
tmp &= ~BOOT_MODE_MASK;
tmp |= mode;
__raw_writel(tmp, REG_CPU_STATE_ADDR + cpu * 4);
writel_relaxed(tmp, REG_CPU_STATE_ADDR + cpu * 4);
}
void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode)
{
unsigned int tmp;
tmp = __raw_readl(REG_CPU_STATE_ADDR + cpu * 4);
tmp = readl_relaxed(REG_CPU_STATE_ADDR + cpu * 4);
tmp &= ~mode;
__raw_writel(tmp, REG_CPU_STATE_ADDR + cpu * 4);
writel_relaxed(tmp, REG_CPU_STATE_ADDR + cpu * 4);
}

3
arch/arm/mach-exynos/headsmp.S
View File

@ -12,12 +12,15 @@
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/assembler.h>
/*
* exynos4 specific entry point for secondary CPUs. This provides
* a "holding pen" into which all secondary cores are held until we're
* ready for them to initialise.
*/
ENTRY(exynos4_secondary_startup)
ARM_BE8(setend be)
mrc p15, 0, r0, c0, c0, 5
and r0, r0, #15
adr r4, 1f

4
arch/arm/mach-exynos/platsmp.c
View File

@ -264,7 +264,7 @@ int exynos_set_boot_addr(u32 core_id, unsigned long boot_addr)
ret = PTR_ERR(boot_reg);
goto fail;
}
__raw_writel(boot_addr, boot_reg);
writel_relaxed(boot_addr, boot_reg);
ret = 0;
}
fail:
@ -289,7 +289,7 @@ int exynos_get_boot_addr(u32 core_id, unsigned long *boot_addr)
ret = PTR_ERR(boot_reg);
goto fail;
}
*boot_addr = __raw_readl(boot_reg);
*boot_addr = readl_relaxed(boot_reg);
ret = 0;
}
fail:

6
arch/arm/mach-exynos/pm.c
View File

@ -132,9 +132,9 @@ static void exynos_set_wakeupmask(long mask)
static void exynos_cpu_set_boot_vector(long flags)
{
__raw_writel(virt_to_phys(exynos_cpu_resume),
exynos_boot_vector_addr());
__raw_writel(flags, exynos_boot_vector_flag());
writel_relaxed(virt_to_phys(exynos_cpu_resume),
exynos_boot_vector_addr());
writel_relaxed(flags, exynos_boot_vector_flag());
}
static int exynos_aftr_finisher(unsigned long flags)

6
arch/arm/mach-exynos/pm_domains.c
View File

@ -70,12 +70,12 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
}
pwr = power_on ? INT_LOCAL_PWR_EN : 0;
__raw_writel(pwr, base);
writel_relaxed(pwr, base);
/* Wait max 1ms */
timeout = 10;
while ((__raw_readl(base + 0x4) & INT_LOCAL_PWR_EN) != pwr) {
while ((readl_relaxed(base + 0x4) & INT_LOCAL_PWR_EN) != pwr) {
if (!timeout) {
op = (power_on) ? "enable" : "disable";
pr_err("Power domain %s %s failed\n", domain->name, op);
@ -185,7 +185,7 @@ static __init int exynos4_pm_init_power_domain(void)
clk_put(pd->oscclk);
no_clk:
on = __raw_readl(pd->base + 0x4) & INT_LOCAL_PWR_EN;
on = readl_relaxed(pd->base + 0x4) & INT_LOCAL_PWR_EN;
pm_genpd_init(&pd->pd, NULL, !on);
of_genpd_add_provider_simple(np, &pd->pd);

12
arch/arm/mach-exynos/suspend.c
View File

@ -301,7 +301,7 @@ static int exynos5420_cpu_suspend(unsigned long arg)
unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
__raw_writel(0x0, sysram_base_addr + EXYNOS5420_CPU_STATE);
writel_relaxed(0x0, sysram_base_addr + EXYNOS5420_CPU_STATE);
if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) {
mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume);
@ -373,8 +373,8 @@ static void exynos5420_pm_prepare(void)
* needs to restore it back in case, the primary cpu fails to
* suspend for any reason.
*/
exynos5420_cpu_state = __raw_readl(sysram_base_addr +
EXYNOS5420_CPU_STATE);
exynos5420_cpu_state = readl_relaxed(sysram_base_addr +
EXYNOS5420_CPU_STATE);
exynos_pm_enter_sleep_mode();
@ -504,11 +504,11 @@ static void exynos5420_pm_resume(void)
/* Restore the CPU0 low power state register */
tmp = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG);
pmu_raw_writel(tmp | S5P_CORE_LOCAL_PWR_EN,
EXYNOS5_ARM_CORE0_SYS_PWR_REG);
EXYNOS5_ARM_CORE0_SYS_PWR_REG);
/* Restore the sysram cpu state register */
__raw_writel(exynos5420_cpu_state,
sysram_base_addr + EXYNOS5420_CPU_STATE);
writel_relaxed(exynos5420_cpu_state,
sysram_base_addr + EXYNOS5420_CPU_STATE);
pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL,
S5P_CENTRAL_SEQ_OPTION);

2
arch/arm/mach-s3c24xx/include/mach/regs-gpio.h
View File

@ -520,7 +520,7 @@
#define S3C24XX_EXTINT1 S3C24XX_GPIOREG2(0x8C)
#define S3C24XX_EXTINT2 S3C24XX_GPIOREG2(0x90)
/* interrupt filtering conrrol for EINT16..EINT23 */
/* interrupt filtering control for EINT16..EINT23 */
#define S3C2410_EINFLT0 S3C2410_GPIOREG(0x94)
#define S3C2410_EINFLT1 S3C2410_GPIOREG(0x98)
#define S3C2410_EINFLT2 S3C2410_GPIOREG(0x9C)

2
arch/arm/mach-s3c24xx/iotiming-s3c2410.c
View File

@ -423,7 +423,7 @@ void s3c2410_iotiming_set(struct s3c_cpufreq_config *cfg,
* @timings: The IO timing information to fill out.
*
* Calculate the @timings timing information from the current frequency
* information in @cfg, and the new frequency configur
* information in @cfg, and the new frequency configuration
* through all the IO banks, reading the state and then updating @iot
* as necessary.
*

2
arch/arm/mach-s3c24xx/mach-n30.c
View File

@ -522,7 +522,7 @@ static void __init n30_hwinit(void)
*
* The pull ups for H6/H7 are enabled on N30 but not on the
* N35/PiN. I suppose is useful for a budget model of the N30
* with no bluetooh. It doesn't hurt to have the pull ups
* with no bluetooth. It doesn't hurt to have the pull ups
* enabled on the N35, so leave them enabled for all models.
*/
__raw_writel(0x0028aaaa, S3C2410_GPHCON);

2
arch/arm/mach-s3c24xx/mach-osiris-dvs.c
View File

@ -143,7 +143,7 @@ static int osiris_dvs_remove(struct platform_device *pdev)
return 0;
}
/* the CONFIG_PM block is so small, it isn't worth actaully compiling it
/* the CONFIG_PM block is so small, it isn't worth actually compiling it
* out if the configuration isn't set. */
static int osiris_dvs_suspend(struct device *dev)

3
arch/arm/mach-s3c24xx/pll-s3c2410.c
View File

@ -32,11 +32,12 @@
#include <plat/cpu.h>
#include <plat/cpu-freq-core.h>
/* This array should be sorted in ascending order of the frequencies */
static struct cpufreq_frequency_table pll_vals_12MHz[] = {
{ .frequency = 34000000, .driver_data = PLLVAL(82, 2, 3), },
{ .frequency = 45000000, .driver_data = PLLVAL(82, 1, 3), },
{ .frequency = 51000000, .driver_data = PLLVAL(161, 3, 3), },
{ .frequency = 48000000, .driver_data = PLLVAL(120, 2, 3), },
{ .frequency = 51000000, .driver_data = PLLVAL(161, 3, 3), },
{ .frequency = 56000000, .driver_data = PLLVAL(142, 2, 3), },
{ .frequency = 68000000, .driver_data = PLLVAL(82, 2, 2), },
{ .frequency = 79000000, .driver_data = PLLVAL(71, 1, 2), },

1
arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c
View File

@ -20,6 +20,7 @@
#include <plat/cpu.h>
#include <plat/cpu-freq-core.h>
/* This array should be sorted in ascending order of the frequencies */
static struct cpufreq_frequency_table s3c2440_plls_12[] = {
{ .frequency = 75000000, .driver_data = PLLVAL(0x75, 3, 3), }, /* FVco 600.000000 */
{ .frequency = 80000000, .driver_data = PLLVAL(0x98, 4, 3), }, /* FVco 640.000000 */

1
arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c
View File

@ -20,6 +20,7 @@
#include <plat/cpu.h>
#include <plat/cpu-freq-core.h>
/* This array should be sorted in ascending order of the frequencies */
static struct cpufreq_frequency_table s3c2440_plls_169344[] = {
{ .frequency = 78019200, .driver_data = PLLVAL(121, 5, 3), }, /* FVco 624.153600 */
{ .frequency = 84067200, .driver_data = PLLVAL(131, 5, 3), }, /* FVco 672.537600 */

2
arch/arm/mach-s3c64xx/include/mach/map.h
View File

@ -99,7 +99,7 @@
#define S3C64XX_PA_USB_HSPHY (0x7C100000)
/* compatibiltiy defines. */
/* compatibility defines. */
#define S3C_PA_TIMER S3C64XX_PA_TIMER
#define S3C_PA_HSMMC0 S3C64XX_PA_HSMMC0
#define S3C_PA_HSMMC1 S3C64XX_PA_HSMMC1

8
arch/arm/plat-samsung/cpu.c
View File

@ -29,14 +29,14 @@ EXPORT_SYMBOL(samsung_rev);
void __init s3c64xx_init_cpu(void)
{
samsung_cpu_id = __raw_readl(S3C_VA_SYS + 0x118);
samsung_cpu_id = readl_relaxed(S3C_VA_SYS + 0x118);
if (!samsung_cpu_id) {
/*
* S3C6400 has the ID register in a different place,
* and needs a write before it can be read.
*/
__raw_writel(0x0, S3C_VA_SYS + 0xA1C);
samsung_cpu_id = __raw_readl(S3C_VA_SYS + 0xA1C);
writel_relaxed(0x0, S3C_VA_SYS + 0xA1C);
samsung_cpu_id = readl_relaxed(S3C_VA_SYS + 0xA1C);
}
samsung_cpu_rev = 0;
@ -46,7 +46,7 @@ void __init s3c64xx_init_cpu(void)
void __init s5p_init_cpu(void __iomem *cpuid_addr)
{
samsung_cpu_id = __raw_readl(cpuid_addr);
samsung_cpu_id = readl_relaxed(cpuid_addr);
samsung_cpu_rev = samsung_cpu_id & 0xFF;
pr_info("Samsung CPU ID: 0x%08lx\n", samsung_cpu_id);

2
arch/arm/plat-samsung/include/plat/cpu-freq-core.h
View File

@ -39,7 +39,7 @@ struct s3c2410_iobank_timing {
unsigned int tacs;
unsigned int tcos;
unsigned int tacc;
unsigned int tcoh; /* nCS hold afrer nOE/nWE */
unsigned int tcoh; /* nCS hold after nOE/nWE */
unsigned int tcah; /* Address hold after nCS */
unsigned char nwait_en; /* nWait enabled for bank. */
};

1
arch/arm/plat-samsung/include/plat/cpu.h
View File

@ -113,6 +113,7 @@ extern void s3c_init_cpu(unsigned long idcode,
extern void s3c24xx_init_io(struct map_desc *mach_desc, int size);
extern void s3c64xx_init_cpu(void);
extern void s5p_init_cpu(void __iomem *cpuid_addr);
extern unsigned int samsung_rev(void);

2
arch/arm/plat-samsung/include/plat/fb-s3c2410.h
View File

@ -48,7 +48,7 @@ struct s3c2410fb_display {
struct s3c2410fb_mach_info {
struct s3c2410fb_display *displays; /* attached diplays info */
struct s3c2410fb_display *displays; /* attached displays info */
unsigned num_displays; /* number of defined displays */
unsigned default_display;

2
arch/arm/plat-samsung/include/plat/gpio-cfg.h
View File

@ -35,7 +35,7 @@ struct samsung_gpio_chip;
* struct samsung_gpio_cfg GPIO configuration
* @cfg_eint: Configuration setting when used for external interrupt source
* @get_pull: Read the current pull configuration for the GPIO
* @set_pull: Set the current pull configuraiton for the GPIO
* @set_pull: Set the current pull configuration for the GPIO
* @set_config: Set the current configuration for the GPIO
* @get_config: Read the current configuration for the GPIO
*

2
arch/arm/plat-samsung/pm-check.c
View File

@ -5,7 +5,7 @@
* http://armlinux.simtec.co.uk
* Ben Dooks <ben@simtec.co.uk>
*
* S3C Power Mangament - suspend/resume memory corruptiuon check.
* S3C Power Mangament - suspend/resume memory corruption check.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as

8
arch/arm/plat-samsung/pm-common.c
View File

@ -31,7 +31,7 @@
void s3c_pm_do_save(struct sleep_save *ptr, int count)
{
for (; count > 0; count--, ptr++) {
ptr->val = __raw_readl(ptr->reg);
ptr->val = readl_relaxed(ptr->reg);
S3C_PMDBG("saved %p value %08lx\n", ptr->reg, ptr->val);
}
}
@ -51,9 +51,9 @@ void s3c_pm_do_restore(const struct sleep_save *ptr, int count)
{
for (; count > 0; count--, ptr++) {
pr_debug("restore %p (restore %08lx, was %08x)\n",
ptr->reg, ptr->val, __raw_readl(ptr->reg));
ptr->reg, ptr->val, readl_relaxed(ptr->reg));
__raw_writel(ptr->val, ptr->reg);
writel_relaxed(ptr->val, ptr->reg);
}
}
@ -71,5 +71,5 @@ void s3c_pm_do_restore(const struct sleep_save *ptr, int count)
void s3c_pm_do_restore_core(const struct sleep_save *ptr, int count)
{
for (; count > 0; count--, ptr++)
__raw_writel(ptr->val, ptr->reg);
writel_relaxed(ptr->val, ptr->reg);
}

2
arch/arm/plat-samsung/watchdog-reset.c
View File

@ -3,7 +3,7 @@
* Copyright (c) 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* Coyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
* Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
*
* Watchdog reset support for Samsung SoCs.
*