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drm/i915: Use the plane state for cursor updates. 

Cursor planes grab the state from plane->state instead of the state
that was passed. The only updates are atomic now, so use the plane_state
that's passed in.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1452164052-21752-6-git-send-email-maarten.lankhorst@linux.intel.com
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
This commit is contained in:
Maarten Lankhorst 2016-01-07 11:54:10 +01:00
parent f285802144
commit 55a08b3f2b
1 changed files with 47 additions and 47 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

94
drivers/gpu/drm/i915/intel_display.c
View File

@ -10112,16 +10112,17 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
return true; return true;
} }
static void i845_update_cursor(struct drm_crtc *crtc, u32 base, bool on) static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
const struct intel_plane_state *plane_state)
{ {
struct drm_device *dev = crtc->dev; struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
uint32_t cntl = 0, size = 0; uint32_t cntl = 0, size = 0;
if (on) { if (plane_state && plane_state->visible) {
unsigned int width = intel_crtc->base.cursor->state->crtc_w; unsigned int width = plane_state->base.crtc_w;
unsigned int height = intel_crtc->base.cursor->state->crtc_h; unsigned int height = plane_state->base.crtc_h;
unsigned int stride = roundup_pow_of_two(width) * 4; unsigned int stride = roundup_pow_of_two(width) * 4;
switch (stride) { switch (stride) {
@ -10174,7 +10175,8 @@ static void i845_update_cursor(struct drm_crtc *crtc, u32 base, bool on)
} }
} }
static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, bool on) static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
const struct intel_plane_state *plane_state)
{ {
struct drm_device *dev = crtc->dev; struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
@ -10182,9 +10184,9 @@ static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, bool on)
int pipe = intel_crtc->pipe; int pipe = intel_crtc->pipe;
uint32_t cntl = 0; uint32_t cntl = 0;
if (on) { if (plane_state && plane_state->visible) {
cntl = MCURSOR_GAMMA_ENABLE; cntl = MCURSOR_GAMMA_ENABLE;
switch (intel_crtc->base.cursor->state->crtc_w) { switch (plane_state->base.crtc_w) {
case 64: case 64:
cntl |= CURSOR_MODE_64_ARGB_AX; cntl |= CURSOR_MODE_64_ARGB_AX;
break; break;
@ -10195,17 +10197,17 @@ static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, bool on)
cntl |= CURSOR_MODE_256_ARGB_AX; cntl |= CURSOR_MODE_256_ARGB_AX;
break; break;
default: default:
MISSING_CASE(intel_crtc->base.cursor->state->crtc_w); MISSING_CASE(plane_state->base.crtc_w);
return; return;
} }
cntl |= pipe << 28; /* Connect to correct pipe */ cntl |= pipe << 28; /* Connect to correct pipe */
if (HAS_DDI(dev)) if (HAS_DDI(dev))
cntl |= CURSOR_PIPE_CSC_ENABLE; cntl |= CURSOR_PIPE_CSC_ENABLE;
}
if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
cntl |= CURSOR_ROTATE_180; cntl |= CURSOR_ROTATE_180;
}
if (intel_crtc->cursor_cntl != cntl) { if (intel_crtc->cursor_cntl != cntl) {
I915_WRITE(CURCNTR(pipe), cntl); I915_WRITE(CURCNTR(pipe), cntl);
@ -10222,44 +10224,45 @@ static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, bool on)
/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
static void intel_crtc_update_cursor(struct drm_crtc *crtc, static void intel_crtc_update_cursor(struct drm_crtc *crtc,
bool on) const struct intel_plane_state *plane_state)
{ {
struct drm_device *dev = crtc->dev; struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
int pipe = intel_crtc->pipe; int pipe = intel_crtc->pipe;
struct drm_plane_state *cursor_state = crtc->cursor->state; u32 base = intel_crtc->cursor_addr;
int x = cursor_state->crtc_x; u32 pos = 0;
int y = cursor_state->crtc_y;
u32 base = 0, pos = 0;
base = intel_crtc->cursor_addr; if (plane_state) {
int x = plane_state->base.crtc_x;
int y = plane_state->base.crtc_y;
if (x < 0) { if (x < 0) {
pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
x = -x; x = -x;
}
pos |= x << CURSOR_X_SHIFT;
if (y < 0) {
pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
y = -y;
}
pos |= y << CURSOR_Y_SHIFT;
/* ILK+ do this automagically */
if (HAS_GMCH_DISPLAY(dev) &&
plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
base += (plane_state->base.crtc_h *
plane_state->base.crtc_w - 1) * 4;
}
} }
pos |= x << CURSOR_X_SHIFT;
if (y < 0) {
pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
y = -y;
}
pos |= y << CURSOR_Y_SHIFT;
I915_WRITE(CURPOS(pipe), pos); I915_WRITE(CURPOS(pipe), pos);
/* ILK+ do this automagically */
if (HAS_GMCH_DISPLAY(dev) &&
crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
base += (cursor_state->crtc_h *
cursor_state->crtc_w - 1) * 4;
}
if (IS_845G(dev) || IS_I865G(dev)) if (IS_845G(dev) || IS_I865G(dev))
i845_update_cursor(crtc, base, on); i845_update_cursor(crtc, base, plane_state);
else else
i9xx_update_cursor(crtc, base, on); i9xx_update_cursor(crtc, base, plane_state);
} }
static bool cursor_size_ok(struct drm_device *dev, static bool cursor_size_ok(struct drm_device *dev,
@ -14259,22 +14262,20 @@ intel_disable_cursor_plane(struct drm_plane *plane,
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
intel_crtc->cursor_addr = 0; intel_crtc->cursor_addr = 0;
intel_crtc_update_cursor(crtc, false); intel_crtc_update_cursor(crtc, NULL);
} }
static void static void
intel_commit_cursor_plane(struct drm_plane *plane, intel_update_cursor_plane(struct drm_plane *plane,
struct intel_plane_state *state) const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *state)
{ {
struct drm_crtc *crtc = state->base.crtc; struct drm_crtc *crtc = crtc_state->base.crtc;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct drm_device *dev = plane->dev; struct drm_device *dev = plane->dev;
struct intel_crtc *intel_crtc;
struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
uint32_t addr; uint32_t addr;
crtc = crtc ? crtc : plane->crtc;
intel_crtc = to_intel_crtc(crtc);
if (!obj) if (!obj)
addr = 0; addr = 0;
else if (!INTEL_INFO(dev)->cursor_needs_physical) else if (!INTEL_INFO(dev)->cursor_needs_physical)
@ -14283,8 +14284,7 @@ intel_commit_cursor_plane(struct drm_plane *plane,
addr = obj->phys_handle->busaddr; addr = obj->phys_handle->busaddr;
intel_crtc->cursor_addr = addr; intel_crtc->cursor_addr = addr;
intel_crtc_update_cursor(crtc, state);
intel_crtc_update_cursor(crtc, state->visible);
} }
static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
@ -14310,7 +14310,7 @@ static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
cursor->plane = pipe; cursor->plane = pipe;
cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
cursor->check_plane = intel_check_cursor_plane; cursor->check_plane = intel_check_cursor_plane;
cursor->commit_plane = intel_commit_cursor_plane; cursor->update_plane = intel_update_cursor_plane;
cursor->disable_plane = intel_disable_cursor_plane; cursor->disable_plane = intel_disable_cursor_plane;
drm_universal_plane_init(dev, &cursor->base, 0, drm_universal_plane_init(dev, &cursor->base, 0,