clk: socfpga: allow for multiple parents on Arria10 periph clocks
There are some Arria10 clocks of type "altr,socfpga-a10-perip-clk" that can have multiple parents. Fix up the __socfpga_periph_init() to call of_clk_parent_fill() that will return the appropriate number of parents. Also, update __socfpga_gate_init() to call of_clk_parent_fill() helper function. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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@ -115,7 +115,6 @@ static void __init __socfpga_gate_init(struct device_node *node,
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const char *parent_name[SOCFPGA_MAX_PARENTS];
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struct clk_init_data init;
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int rc;
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int i = 0;
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socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
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if (WARN_ON(!socfpga_clk))
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@ -167,12 +166,9 @@ static void __init __socfpga_gate_init(struct device_node *node,
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init.name = clk_name;
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init.ops = ops;
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init.flags = 0;
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while (i < SOCFPGA_MAX_PARENTS && (parent_name[i] =
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of_clk_get_parent_name(node, i)) != NULL)
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i++;
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init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS);
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init.parent_names = parent_name;
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init.num_parents = i;
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socfpga_clk->hw.hw.init = &init;
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clk = clk_register(NULL, &socfpga_clk->hw.hw);
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@ -74,7 +74,7 @@ static __init void __socfpga_periph_init(struct device_node *node,
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struct clk *clk;
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struct socfpga_periph_clk *periph_clk;
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const char *clk_name = node->name;
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const char *parent_name;
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const char *parent_name[SOCFPGA_MAX_PARENTS];
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struct clk_init_data init;
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int rc;
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u32 fixed_div;
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@ -109,9 +109,8 @@ static __init void __socfpga_periph_init(struct device_node *node,
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init.ops = ops;
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init.flags = 0;
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parent_name = of_clk_get_parent_name(node, 0);
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init.num_parents = 1;
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init.parent_names = &parent_name;
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init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS);
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init.parent_names = parent_name;
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periph_clk->hw.hw.init = &init;
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