net: stmmac: Initial support for TBS
Adds the initial hooks for TBS support. This needs a 32 byte descriptor in order for it to work with current HW. Adds all the logic for Enhanced Descriptors in main core but no HW related logic for now. Changes from v2: - Use bitfield for TBS status / support (Jakub) - Remove unneeded cache alignment (Jakub) - Fix checkpatch issues Signed-off-by: Jose Abreu <Jose.Abreu@synopsys.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jose Abreu
Jakub Kicinski
parent
ab9837b5ed
commit
579a25a854
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@ -171,6 +171,15 @@ struct dma_extended_desc {
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__le32 des7; /* Tx/Rx Timestamp High */
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};
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/* Enhanced descriptor for TBS */
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struct dma_edesc {
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__le32 des4;
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__le32 des5;
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__le32 des6;
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__le32 des7;
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struct dma_desc basic;
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};
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/* Transmit checksum insertion control */
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#define TX_CIC_FULL 3 /* Include IP header and pseudoheader */
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@ -29,6 +29,7 @@ struct stmmac_extra_stats;
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struct stmmac_safety_stats;
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struct dma_desc;
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struct dma_extended_desc;
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struct dma_edesc;
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/* Descriptors helpers */
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struct stmmac_desc_ops {
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@ -95,6 +96,7 @@ struct stmmac_desc_ops {
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void (*set_vlan_tag)(struct dma_desc *p, u16 tag, u16 inner_tag,
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u32 inner_type);
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void (*set_vlan)(struct dma_desc *p, u32 type);
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void (*set_tbs)(struct dma_edesc *p, u32 sec, u32 nsec);
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};
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#define stmmac_init_rx_desc(__priv, __args...) \
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@ -157,6 +159,8 @@ struct stmmac_desc_ops {
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stmmac_do_void_callback(__priv, desc, set_vlan_tag, __args)
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#define stmmac_set_desc_vlan(__priv, __args...) \
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stmmac_do_void_callback(__priv, desc, set_vlan, __args)
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#define stmmac_set_desc_tbs(__priv, __args...) \
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stmmac_do_void_callback(__priv, desc, set_tbs, __args)
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struct stmmac_dma_cfg;
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struct dma_features;
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@ -210,6 +214,7 @@ struct stmmac_dma_ops {
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void (*qmode)(void __iomem *ioaddr, u32 channel, u8 qmode);
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void (*set_bfsize)(void __iomem *ioaddr, int bfsize, u32 chan);
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void (*enable_sph)(void __iomem *ioaddr, bool en, u32 chan);
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int (*enable_tbs)(void __iomem *ioaddr, bool en, u32 chan);
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};
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#define stmmac_reset(__priv, __args...) \
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@ -268,6 +273,8 @@ struct stmmac_dma_ops {
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stmmac_do_void_callback(__priv, dma, set_bfsize, __args)
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#define stmmac_enable_sph(__priv, __args...) \
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stmmac_do_void_callback(__priv, dma, enable_sph, __args)
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#define stmmac_enable_tbs(__priv, __args...) \
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stmmac_do_callback(__priv, dma, enable_tbs, __args)
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struct mac_device_info;
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struct net_device;
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@ -39,13 +39,18 @@ struct stmmac_tx_info {
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bool is_jumbo;
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};
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#define STMMAC_TBS_AVAIL BIT(0)
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#define STMMAC_TBS_EN BIT(1)
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/* Frequently used values are kept adjacent for cache effect */
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struct stmmac_tx_queue {
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u32 tx_count_frames;
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int tbs;
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struct timer_list txtimer;
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u32 queue_index;
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struct stmmac_priv *priv_data;
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struct dma_extended_desc *dma_etx ____cacheline_aligned_in_smp;
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struct dma_edesc *dma_entx;
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struct dma_desc *dma_tx;
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struct sk_buff **tx_skbuff;
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struct stmmac_tx_info *tx_skbuff_dma;
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@ -1090,6 +1090,8 @@ static void stmmac_display_tx_rings(struct stmmac_priv *priv)
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if (priv->extend_desc)
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head_tx = (void *)tx_q->dma_etx;
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else if (tx_q->tbs & STMMAC_TBS_AVAIL)
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head_tx = (void *)tx_q->dma_entx;
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else
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head_tx = (void *)tx_q->dma_tx;
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@ -1163,13 +1165,19 @@ static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue)
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int i;
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/* Clear the TX descriptors */
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for (i = 0; i < DMA_TX_SIZE; i++)
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for (i = 0; i < DMA_TX_SIZE; i++) {
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int last = (i == (DMA_TX_SIZE - 1));
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struct dma_desc *p;
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if (priv->extend_desc)
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stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic,
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priv->mode, (i == DMA_TX_SIZE - 1));
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p = &tx_q->dma_etx[i].basic;
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else if (tx_q->tbs & STMMAC_TBS_AVAIL)
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p = &tx_q->dma_entx[i].basic;
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else
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stmmac_init_tx_desc(priv, &tx_q->dma_tx[i],
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priv->mode, (i == DMA_TX_SIZE - 1));
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p = &tx_q->dma_tx[i];
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stmmac_init_tx_desc(priv, p, priv->mode, last);
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}
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}
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/**
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@ -1383,7 +1391,7 @@ static int init_dma_tx_desc_rings(struct net_device *dev)
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if (priv->extend_desc)
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stmmac_mode_init(priv, tx_q->dma_etx,
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tx_q->dma_tx_phy, DMA_TX_SIZE, 1);
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else
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else if (!(tx_q->tbs & STMMAC_TBS_AVAIL))
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stmmac_mode_init(priv, tx_q->dma_tx,
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tx_q->dma_tx_phy, DMA_TX_SIZE, 0);
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}
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@ -1392,6 +1400,8 @@ static int init_dma_tx_desc_rings(struct net_device *dev)
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struct dma_desc *p;
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if (priv->extend_desc)
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p = &((tx_q->dma_etx + i)->basic);
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else if (tx_q->tbs & STMMAC_TBS_AVAIL)
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p = &((tx_q->dma_entx + i)->basic);
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else
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p = tx_q->dma_tx + i;
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@ -1511,19 +1521,26 @@ static void free_dma_tx_desc_resources(struct stmmac_priv *priv)
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/* Free TX queue resources */
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for (queue = 0; queue < tx_count; queue++) {
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struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
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size_t size;
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void *addr;
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/* Release the DMA TX socket buffers */
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dma_free_tx_skbufs(priv, queue);
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/* Free DMA regions of consistent memory previously allocated */
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if (!priv->extend_desc)
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dma_free_coherent(priv->device,
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DMA_TX_SIZE * sizeof(struct dma_desc),
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tx_q->dma_tx, tx_q->dma_tx_phy);
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else
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dma_free_coherent(priv->device, DMA_TX_SIZE *
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sizeof(struct dma_extended_desc),
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tx_q->dma_etx, tx_q->dma_tx_phy);
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if (priv->extend_desc) {
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size = sizeof(struct dma_extended_desc);
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addr = tx_q->dma_etx;
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} else if (tx_q->tbs & STMMAC_TBS_AVAIL) {
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size = sizeof(struct dma_edesc);
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addr = tx_q->dma_entx;
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} else {
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size = sizeof(struct dma_desc);
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addr = tx_q->dma_tx;
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}
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size *= DMA_TX_SIZE;
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dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy);
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kfree(tx_q->tx_skbuff_dma);
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kfree(tx_q->tx_skbuff);
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@ -1616,6 +1633,8 @@ static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv)
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/* TX queues buffers and DMA */
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for (queue = 0; queue < tx_count; queue++) {
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struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
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size_t size;
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void *addr;
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tx_q->queue_index = queue;
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tx_q->priv_data = priv;
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@ -1632,28 +1651,32 @@ static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv)
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if (!tx_q->tx_skbuff)
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goto err_dma;
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if (priv->extend_desc) {
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tx_q->dma_etx = dma_alloc_coherent(priv->device,
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DMA_TX_SIZE * sizeof(struct dma_extended_desc),
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&tx_q->dma_tx_phy,
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GFP_KERNEL);
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if (!tx_q->dma_etx)
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goto err_dma;
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} else {
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tx_q->dma_tx = dma_alloc_coherent(priv->device,
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DMA_TX_SIZE * sizeof(struct dma_desc),
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&tx_q->dma_tx_phy,
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GFP_KERNEL);
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if (!tx_q->dma_tx)
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goto err_dma;
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}
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if (priv->extend_desc)
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size = sizeof(struct dma_extended_desc);
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else if (tx_q->tbs & STMMAC_TBS_AVAIL)
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size = sizeof(struct dma_edesc);
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else
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size = sizeof(struct dma_desc);
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size *= DMA_TX_SIZE;
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addr = dma_alloc_coherent(priv->device, size,
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&tx_q->dma_tx_phy, GFP_KERNEL);
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if (!addr)
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goto err_dma;
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if (priv->extend_desc)
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tx_q->dma_etx = addr;
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else if (tx_q->tbs & STMMAC_TBS_AVAIL)
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tx_q->dma_entx = addr;
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else
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tx_q->dma_tx = addr;
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}
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return 0;
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err_dma:
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free_dma_tx_desc_resources(priv);
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return ret;
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}
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@ -1885,6 +1908,8 @@ static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue)
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if (priv->extend_desc)
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p = (struct dma_desc *)(tx_q->dma_etx + entry);
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else if (tx_q->tbs & STMMAC_TBS_AVAIL)
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p = &tx_q->dma_entx[entry].basic;
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else
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p = tx_q->dma_tx + entry;
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@ -1983,19 +2008,12 @@ static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue)
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static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan)
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{
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struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
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int i;
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netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan));
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stmmac_stop_tx_dma(priv, chan);
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dma_free_tx_skbufs(priv, chan);
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for (i = 0; i < DMA_TX_SIZE; i++)
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if (priv->extend_desc)
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stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic,
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priv->mode, (i == DMA_TX_SIZE - 1));
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else
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stmmac_init_tx_desc(priv, &tx_q->dma_tx[i],
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priv->mode, (i == DMA_TX_SIZE - 1));
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stmmac_clear_tx_descriptors(priv, chan);
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tx_q->dirty_tx = 0;
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tx_q->cur_tx = 0;
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tx_q->mss = 0;
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@ -2632,6 +2650,14 @@ static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
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if (priv->dma_cap.vlins)
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stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT);
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/* TBS */
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for (chan = 0; chan < tx_cnt; chan++) {
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struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
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int enable = tx_q->tbs & STMMAC_TBS_AVAIL;
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stmmac_enable_tbs(priv, priv->ioaddr, enable, chan);
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}
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/* Start the ball rolling... */
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stmmac_start_all_dma(priv);
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@ -2689,6 +2715,16 @@ static int stmmac_open(struct net_device *dev)
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priv->rx_copybreak = STMMAC_RX_COPYBREAK;
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/* Earlier check for TBS */
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for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) {
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struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
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int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en;
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tx_q->tbs |= tbs_en ? STMMAC_TBS_AVAIL : 0;
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if (stmmac_enable_tbs(priv, priv->ioaddr, tbs_en, chan))
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tx_q->tbs &= ~STMMAC_TBS_AVAIL;
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}
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ret = alloc_dma_desc_resources(priv);
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if (ret < 0) {
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netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n",
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@ -2837,7 +2873,11 @@ static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb,
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tag = skb_vlan_tag_get(skb);
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p = tx_q->dma_tx + tx_q->cur_tx;
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if (tx_q->tbs & STMMAC_TBS_AVAIL)
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p = &tx_q->dma_entx[tx_q->cur_tx].basic;
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else
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p = &tx_q->dma_tx[tx_q->cur_tx];
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if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type))
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return false;
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@ -2872,7 +2912,11 @@ static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des,
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tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
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WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
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desc = tx_q->dma_tx + tx_q->cur_tx;
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if (tx_q->tbs & STMMAC_TBS_AVAIL)
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desc = &tx_q->dma_entx[tx_q->cur_tx].basic;
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else
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desc = &tx_q->dma_tx[tx_q->cur_tx];
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curr_addr = des + (total_len - tmp_len);
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if (priv->dma_cap.addr64 <= 32)
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@ -2923,13 +2967,13 @@ static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
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{
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struct dma_desc *desc, *first, *mss_desc = NULL;
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struct stmmac_priv *priv = netdev_priv(dev);
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int desc_size, tmp_pay_len = 0, first_tx;
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int nfrags = skb_shinfo(skb)->nr_frags;
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u32 queue = skb_get_queue_mapping(skb);
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unsigned int first_entry, tx_packets;
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int tmp_pay_len = 0, first_tx;
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struct stmmac_tx_queue *tx_q;
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u8 proto_hdr_len, hdr;
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bool has_vlan, set_ic;
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u8 proto_hdr_len, hdr;
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u32 pay_len, mss;
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dma_addr_t des;
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int i;
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@ -2966,7 +3010,11 @@ static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
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/* set new MSS value if needed */
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if (mss != tx_q->mss) {
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mss_desc = tx_q->dma_tx + tx_q->cur_tx;
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if (tx_q->tbs & STMMAC_TBS_AVAIL)
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mss_desc = &tx_q->dma_entx[tx_q->cur_tx].basic;
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else
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mss_desc = &tx_q->dma_tx[tx_q->cur_tx];
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stmmac_set_mss(priv, mss_desc, mss);
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tx_q->mss = mss;
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tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
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@ -2986,7 +3034,10 @@ static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
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first_entry = tx_q->cur_tx;
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WARN_ON(tx_q->tx_skbuff[first_entry]);
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desc = tx_q->dma_tx + first_entry;
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if (tx_q->tbs & STMMAC_TBS_AVAIL)
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desc = &tx_q->dma_entx[first_entry].basic;
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else
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desc = &tx_q->dma_tx[first_entry];
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first = desc;
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if (has_vlan)
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@ -3058,7 +3109,11 @@ static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
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set_ic = false;
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if (set_ic) {
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desc = &tx_q->dma_tx[tx_q->cur_tx];
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if (tx_q->tbs & STMMAC_TBS_AVAIL)
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desc = &tx_q->dma_entx[tx_q->cur_tx].basic;
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else
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desc = &tx_q->dma_tx[tx_q->cur_tx];
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tx_q->tx_count_frames = 0;
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stmmac_set_tx_ic(priv, desc);
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priv->xstats.tx_set_ic_bit++;
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@ -3121,16 +3176,18 @@ static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
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pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
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__func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
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tx_q->cur_tx, first, nfrags);
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stmmac_display_ring(priv, (void *)tx_q->dma_tx, DMA_TX_SIZE, 0);
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pr_info(">>> frame to be transmitted: ");
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print_pkt(skb->data, skb_headlen(skb));
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}
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netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
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tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc));
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||||
if (tx_q->tbs & STMMAC_TBS_AVAIL)
|
||||
desc_size = sizeof(struct dma_edesc);
|
||||
else
|
||||
desc_size = sizeof(struct dma_desc);
|
||||
|
||||
tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size);
|
||||
stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
|
||||
stmmac_tx_timer_arm(priv, queue);
|
||||
|
||||
|
|
@ -3160,10 +3217,11 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
|
|||
u32 queue = skb_get_queue_mapping(skb);
|
||||
int nfrags = skb_shinfo(skb)->nr_frags;
|
||||
int gso = skb_shinfo(skb)->gso_type;
|
||||
struct dma_edesc *tbs_desc = NULL;
|
||||
int entry, desc_size, first_tx;
|
||||
struct dma_desc *desc, *first;
|
||||
struct stmmac_tx_queue *tx_q;
|
||||
bool has_vlan, set_ic;
|
||||
int entry, first_tx;
|
||||
dma_addr_t des;
|
||||
|
||||
tx_q = &priv->tx_queue[queue];
|
||||
|
|
@ -3203,6 +3261,8 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
|
|||
|
||||
if (likely(priv->extend_desc))
|
||||
desc = (struct dma_desc *)(tx_q->dma_etx + entry);
|
||||
else if (tx_q->tbs & STMMAC_TBS_AVAIL)
|
||||
desc = &tx_q->dma_entx[entry].basic;
|
||||
else
|
||||
desc = tx_q->dma_tx + entry;
|
||||
|
||||
|
|
@ -3232,6 +3292,8 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
|
|||
|
||||
if (likely(priv->extend_desc))
|
||||
desc = (struct dma_desc *)(tx_q->dma_etx + entry);
|
||||
else if (tx_q->tbs & STMMAC_TBS_AVAIL)
|
||||
desc = &tx_q->dma_entx[entry].basic;
|
||||
else
|
||||
desc = tx_q->dma_tx + entry;
|
||||
|
||||
|
|
@ -3278,6 +3340,8 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
|
|||
if (set_ic) {
|
||||
if (likely(priv->extend_desc))
|
||||
desc = &tx_q->dma_etx[entry].basic;
|
||||
else if (tx_q->tbs & STMMAC_TBS_AVAIL)
|
||||
desc = &tx_q->dma_entx[entry].basic;
|
||||
else
|
||||
desc = &tx_q->dma_tx[entry];
|
||||
|
||||
|
|
@ -3295,20 +3359,11 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
|
|||
tx_q->cur_tx = entry;
|
||||
|
||||
if (netif_msg_pktdata(priv)) {
|
||||
void *tx_head;
|
||||
|
||||
netdev_dbg(priv->dev,
|
||||
"%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
|
||||
__func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
|
||||
entry, first, nfrags);
|
||||
|
||||
if (priv->extend_desc)
|
||||
tx_head = (void *)tx_q->dma_etx;
|
||||
else
|
||||
tx_head = (void *)tx_q->dma_tx;
|
||||
|
||||
stmmac_display_ring(priv, tx_head, DMA_TX_SIZE, false);
|
||||
|
||||
netdev_dbg(priv->dev, ">>> frame to be transmitted: ");
|
||||
print_pkt(skb->data, skb->len);
|
||||
}
|
||||
|
|
@ -3354,12 +3409,19 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
|
|||
|
||||
/* Prepare the first descriptor setting the OWN bit too */
|
||||
stmmac_prepare_tx_desc(priv, first, 1, nopaged_len,
|
||||
csum_insertion, priv->mode, 1, last_segment,
|
||||
csum_insertion, priv->mode, 0, last_segment,
|
||||
skb->len);
|
||||
} else {
|
||||
stmmac_set_tx_owner(priv, first);
|
||||
}
|
||||
|
||||
if (tx_q->tbs & STMMAC_TBS_EN) {
|
||||
struct timespec64 ts = ns_to_timespec64(skb->tstamp);
|
||||
|
||||
tbs_desc = &tx_q->dma_entx[first_entry];
|
||||
stmmac_set_desc_tbs(priv, tbs_desc, ts.tv_sec, ts.tv_nsec);
|
||||
}
|
||||
|
||||
stmmac_set_tx_owner(priv, first);
|
||||
|
||||
/* The own bit must be the latest setting done when prepare the
|
||||
* descriptor and then barrier is needed to make sure that
|
||||
* all is coherent before granting the DMA engine.
|
||||
|
|
@ -3370,7 +3432,14 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
|
|||
|
||||
stmmac_enable_dma_transmission(priv, priv->ioaddr);
|
||||
|
||||
tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc));
|
||||
if (likely(priv->extend_desc))
|
||||
desc_size = sizeof(struct dma_extended_desc);
|
||||
else if (tx_q->tbs & STMMAC_TBS_AVAIL)
|
||||
desc_size = sizeof(struct dma_edesc);
|
||||
else
|
||||
desc_size = sizeof(struct dma_desc);
|
||||
|
||||
tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size);
|
||||
stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
|
||||
stmmac_tx_timer_arm(priv, queue);
|
||||
|
||||
|
|
@ -4193,7 +4262,7 @@ static int stmmac_rings_status_show(struct seq_file *seq, void *v)
|
|||
seq_printf(seq, "Extended descriptor ring:\n");
|
||||
sysfs_display_ring((void *)tx_q->dma_etx,
|
||||
DMA_TX_SIZE, 1, seq);
|
||||
} else {
|
||||
} else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) {
|
||||
seq_printf(seq, "Descriptor ring:\n");
|
||||
sysfs_display_ring((void *)tx_q->dma_tx,
|
||||
DMA_TX_SIZE, 0, seq);
|
||||
|
|
|
|||
|
|
@ -139,6 +139,7 @@ struct stmmac_txq_cfg {
|
|||
u32 low_credit;
|
||||
bool use_prio;
|
||||
u32 prio;
|
||||
int tbs_en;
|
||||
};
|
||||
|
||||
struct plat_stmmacenet_data {
|
||||
|
|
|
|||
Loading…
Reference in New Issue