ASoC: es8328: Fix ADC format setup
The ADCCONTROL4 and DACCONTROL1 registers are similar but not identical, with the DACCONTROL1 having each field starting one bit higher than ADCCONTROL4. Instead of introducing a magic shift, add new constants for the values in ADCCONTROL4 and use a second variable to setup the ADC. Signed-off-by: John Keeping <john@metanate.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -493,7 +493,8 @@ static int es8328_set_dai_fmt(struct snd_soc_dai *codec_dai,
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unsigned int fmt)
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{
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struct snd_soc_codec *codec = codec_dai->codec;
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u8 mode = ES8328_DACCONTROL1_DACWL_16;
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u8 dac_mode = ES8328_DACCONTROL1_DACWL_16;
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u8 adc_mode = ES8328_ADCCONTROL4_ADCWL_16;
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/* set master/slave audio interface */
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if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBM_CFM)
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@ -502,13 +503,16 @@ static int es8328_set_dai_fmt(struct snd_soc_dai *codec_dai,
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/* interface format */
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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mode |= ES8328_DACCONTROL1_DACFORMAT_I2S;
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dac_mode |= ES8328_DACCONTROL1_DACFORMAT_I2S;
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adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_I2S;
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break;
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case SND_SOC_DAIFMT_RIGHT_J:
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mode |= ES8328_DACCONTROL1_DACFORMAT_RJUST;
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dac_mode |= ES8328_DACCONTROL1_DACFORMAT_RJUST;
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adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_RJUST;
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break;
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case SND_SOC_DAIFMT_LEFT_J:
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mode |= ES8328_DACCONTROL1_DACFORMAT_LJUST;
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dac_mode |= ES8328_DACCONTROL1_DACFORMAT_LJUST;
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adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_LJUST;
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break;
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default:
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return -EINVAL;
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@ -518,8 +522,8 @@ static int es8328_set_dai_fmt(struct snd_soc_dai *codec_dai,
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if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF)
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return -EINVAL;
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snd_soc_write(codec, ES8328_DACCONTROL1, mode);
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snd_soc_write(codec, ES8328_ADCCONTROL4, mode);
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snd_soc_write(codec, ES8328_DACCONTROL1, dac_mode);
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snd_soc_write(codec, ES8328_ADCCONTROL4, adc_mode);
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/* Master serial port mode, with BCLK generated automatically */
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snd_soc_update_bits(codec, ES8328_MASTERMODE,
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@ -84,7 +84,22 @@ int es8328_probe(struct device *dev, struct regmap *regmap);
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#define ES8328_ADCCONTROL1 0x09
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#define ES8328_ADCCONTROL2 0x0a
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#define ES8328_ADCCONTROL3 0x0b
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#define ES8328_ADCCONTROL4 0x0c
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#define ES8328_ADCCONTROL4_ADCFORMAT_I2S (0 << 0)
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#define ES8328_ADCCONTROL4_ADCFORMAT_LJUST (1 << 0)
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#define ES8328_ADCCONTROL4_ADCFORMAT_RJUST (2 << 0)
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#define ES8328_ADCCONTROL4_ADCFORMAT_PCM (3 << 0)
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#define ES8328_ADCCONTROL4_ADCWL_24 (0 << 2)
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#define ES8328_ADCCONTROL4_ADCWL_20 (1 << 2)
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#define ES8328_ADCCONTROL4_ADCWL_18 (2 << 2)
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#define ES8328_ADCCONTROL4_ADCWL_16 (3 << 2)
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#define ES8328_ADCCONTROL4_ADCWL_32 (4 << 2)
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#define ES8328_ADCCONTROL4_ADCLRP_I2S_POL_NORMAL (0 << 5)
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#define ES8328_ADCCONTROL4_ADCLRP_I2S_POL_INV (1 << 5)
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#define ES8328_ADCCONTROL4_ADCLRP_PCM_MSB_CLK2 (0 << 5)
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#define ES8328_ADCCONTROL4_ADCLRP_PCM_MSB_CLK1 (1 << 5)
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#define ES8328_ADCCONTROL5 0x0d
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#define ES8328_ADCCONTROL5_RATEMASK (0x1f << 0)
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