drm/i915: Skip modeset for cdclk changes if possible
If we have only a single active pipe and the cdclk change only requires the cd2x divider to be updated bxt+ can do the update with forcing a full modeset on the pipe. Try to hook that up. v2: - Wait for vblank after an optimized CDCLK change. - Avoid optimization if the pipe needs a modeset (or was disabled). - Split CDCLK change to a pre/post plane update step. v3: - Use correct version of CDCLK state as old state. (Ville) - Remove unused intel_cdclk_can_skip_modeset() v4: - For consistency call intel_set_cdclk_post_plane_update() only during modesets (and not fastsets). v5: - Remove the logic to update the CD2X divider on-the-fly on ICL, since only a divider of 1 is supported there. Clint also noticed that the pipe select bits in CDCLK_CTL are oddly defined on ICL, it's not clear yet whether that's only an error in the specification. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Abhay Kumar <abhay.kumar@intel.com> Tested-by: Abhay Kumar <abhay.kumar@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190327101321.3095-1-imre.deak@intel.com
This commit is contained in:
Ville Syrjälä
Imre Deak
parent
2b21dfbeee
commit
59f9e9cab3
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@ -282,7 +282,8 @@ struct drm_i915_display_funcs {
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void (*get_cdclk)(struct drm_i915_private *dev_priv,
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struct intel_cdclk_state *cdclk_state);
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void (*set_cdclk)(struct drm_i915_private *dev_priv,
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const struct intel_cdclk_state *cdclk_state);
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const struct intel_cdclk_state *cdclk_state,
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enum pipe pipe);
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int (*get_fifo_size)(struct drm_i915_private *dev_priv,
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enum i9xx_plane_id i9xx_plane);
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int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
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@ -517,7 +517,8 @@ static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
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}
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static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
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const struct intel_cdclk_state *cdclk_state)
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const struct intel_cdclk_state *cdclk_state,
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enum pipe pipe)
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{
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int cdclk = cdclk_state->cdclk;
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u32 val, cmd = cdclk_state->voltage_level;
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@ -599,7 +600,8 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
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}
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static void chv_set_cdclk(struct drm_i915_private *dev_priv,
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const struct intel_cdclk_state *cdclk_state)
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const struct intel_cdclk_state *cdclk_state,
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enum pipe pipe)
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{
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int cdclk = cdclk_state->cdclk;
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u32 val, cmd = cdclk_state->voltage_level;
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@ -698,7 +700,8 @@ static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
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}
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static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
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const struct intel_cdclk_state *cdclk_state)
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const struct intel_cdclk_state *cdclk_state,
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enum pipe pipe)
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{
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int cdclk = cdclk_state->cdclk;
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u32 val;
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@ -988,7 +991,8 @@ static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
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}
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static void skl_set_cdclk(struct drm_i915_private *dev_priv,
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const struct intel_cdclk_state *cdclk_state)
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const struct intel_cdclk_state *cdclk_state,
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enum pipe pipe)
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{
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int cdclk = cdclk_state->cdclk;
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int vco = cdclk_state->vco;
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@ -1159,7 +1163,7 @@ void skl_init_cdclk(struct drm_i915_private *dev_priv)
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cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco);
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cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
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skl_set_cdclk(dev_priv, &cdclk_state);
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skl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
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}
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/**
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@ -1177,7 +1181,7 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
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cdclk_state.vco = 0;
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cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
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skl_set_cdclk(dev_priv, &cdclk_state);
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skl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
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}
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static int bxt_calc_cdclk(int min_cdclk)
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@ -1356,7 +1360,8 @@ static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
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}
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static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
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const struct intel_cdclk_state *cdclk_state)
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const struct intel_cdclk_state *cdclk_state,
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enum pipe pipe)
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{
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int cdclk = cdclk_state->cdclk;
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int vco = cdclk_state->vco;
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@ -1409,11 +1414,10 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
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bxt_de_pll_enable(dev_priv, vco);
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val = divider | skl_cdclk_decimal(cdclk);
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/*
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* FIXME if only the cd2x divider needs changing, it could be done
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* without shutting off the pipe (if only one pipe is active).
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*/
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val |= BXT_CDCLK_CD2X_PIPE_NONE;
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if (pipe == INVALID_PIPE)
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val |= BXT_CDCLK_CD2X_PIPE_NONE;
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else
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val |= BXT_CDCLK_CD2X_PIPE(pipe);
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/*
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* Disable SSA Precharge when CD clock frequency < 500 MHz,
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* enable otherwise.
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@ -1422,6 +1426,9 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
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val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
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I915_WRITE(CDCLK_CTL, val);
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if (pipe != INVALID_PIPE)
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intel_wait_for_vblank(dev_priv, pipe);
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mutex_lock(&dev_priv->pcu_lock);
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/*
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* The timeout isn't specified, the 2ms used here is based on
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@ -1526,7 +1533,7 @@ void bxt_init_cdclk(struct drm_i915_private *dev_priv)
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}
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cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);
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bxt_set_cdclk(dev_priv, &cdclk_state);
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bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
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}
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/**
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@ -1544,7 +1551,7 @@ void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
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cdclk_state.vco = 0;
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cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);
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bxt_set_cdclk(dev_priv, &cdclk_state);
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bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
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}
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static int cnl_calc_cdclk(int min_cdclk)
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@ -1664,7 +1671,8 @@ static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
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}
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static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
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const struct intel_cdclk_state *cdclk_state)
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const struct intel_cdclk_state *cdclk_state,
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enum pipe pipe)
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{
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int cdclk = cdclk_state->cdclk;
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int vco = cdclk_state->vco;
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@ -1705,13 +1713,15 @@ static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
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cnl_cdclk_pll_enable(dev_priv, vco);
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val = divider | skl_cdclk_decimal(cdclk);
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/*
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* FIXME if only the cd2x divider needs changing, it could be done
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* without shutting off the pipe (if only one pipe is active).
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*/
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val |= BXT_CDCLK_CD2X_PIPE_NONE;
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if (pipe == INVALID_PIPE)
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val |= BXT_CDCLK_CD2X_PIPE_NONE;
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else
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val |= BXT_CDCLK_CD2X_PIPE(pipe);
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I915_WRITE(CDCLK_CTL, val);
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if (pipe != INVALID_PIPE)
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intel_wait_for_vblank(dev_priv, pipe);
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/* inform PCU of the change */
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mutex_lock(&dev_priv->pcu_lock);
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sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
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@ -1848,7 +1858,8 @@ static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
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}
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static void icl_set_cdclk(struct drm_i915_private *dev_priv,
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const struct intel_cdclk_state *cdclk_state)
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const struct intel_cdclk_state *cdclk_state,
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enum pipe pipe)
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{
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unsigned int cdclk = cdclk_state->cdclk;
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unsigned int vco = cdclk_state->vco;
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@ -1873,6 +1884,11 @@ static void icl_set_cdclk(struct drm_i915_private *dev_priv,
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if (dev_priv->cdclk.hw.vco != vco)
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cnl_cdclk_pll_enable(dev_priv, vco);
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/*
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* On ICL CD2X_DIV can only be 1, so we'll never end up changing the
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* divider here synchronized to a pipe while CDCLK is on, nor will we
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* need the corresponding vblank wait.
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*/
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I915_WRITE(CDCLK_CTL, ICL_CDCLK_CD2X_PIPE_NONE |
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skl_cdclk_decimal(cdclk));
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@ -2003,7 +2019,7 @@ void icl_init_cdclk(struct drm_i915_private *dev_priv)
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sanitized_state.voltage_level =
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icl_calc_voltage_level(sanitized_state.cdclk);
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icl_set_cdclk(dev_priv, &sanitized_state);
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icl_set_cdclk(dev_priv, &sanitized_state, INVALID_PIPE);
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}
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/**
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@ -2021,7 +2037,7 @@ void icl_uninit_cdclk(struct drm_i915_private *dev_priv)
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cdclk_state.vco = 0;
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cdclk_state.voltage_level = icl_calc_voltage_level(cdclk_state.cdclk);
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icl_set_cdclk(dev_priv, &cdclk_state);
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icl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
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}
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/**
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@ -2049,7 +2065,7 @@ void cnl_init_cdclk(struct drm_i915_private *dev_priv)
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cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
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cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
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cnl_set_cdclk(dev_priv, &cdclk_state);
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cnl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
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}
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/**
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@ -2067,7 +2083,7 @@ void cnl_uninit_cdclk(struct drm_i915_private *dev_priv)
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cdclk_state.vco = 0;
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cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
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cnl_set_cdclk(dev_priv, &cdclk_state);
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cnl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
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}
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/**
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@ -2086,6 +2102,27 @@ bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
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a->ref != b->ref;
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}
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/**
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* intel_cdclk_needs_cd2x_update - Determine if two CDCLK states require a cd2x divider update
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* @a: first CDCLK state
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* @b: second CDCLK state
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*
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* Returns:
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* True if the CDCLK states require just a cd2x divider update, false if not.
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*/
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bool intel_cdclk_needs_cd2x_update(struct drm_i915_private *dev_priv,
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const struct intel_cdclk_state *a,
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const struct intel_cdclk_state *b)
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{
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/* Older hw doesn't have the capability */
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if (INTEL_GEN(dev_priv) < 10 && !IS_GEN9_LP(dev_priv))
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return false;
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return a->cdclk != b->cdclk &&
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a->vco == b->vco &&
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a->ref == b->ref;
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}
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/**
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* intel_cdclk_changed - Determine if two CDCLK states are different
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* @a: first CDCLK state
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@ -2134,12 +2171,14 @@ void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
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* intel_set_cdclk - Push the CDCLK state to the hardware
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* @dev_priv: i915 device
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* @cdclk_state: new CDCLK state
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* @pipe: pipe with which to synchronize the update
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*
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* Program the hardware based on the passed in CDCLK state,
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* if necessary.
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*/
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void intel_set_cdclk(struct drm_i915_private *dev_priv,
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const struct intel_cdclk_state *cdclk_state)
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static void intel_set_cdclk(struct drm_i915_private *dev_priv,
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const struct intel_cdclk_state *cdclk_state,
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enum pipe pipe)
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{
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if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state))
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return;
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@ -2149,7 +2188,7 @@ void intel_set_cdclk(struct drm_i915_private *dev_priv,
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intel_dump_cdclk_state(cdclk_state, "Changing CDCLK to");
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dev_priv->display.set_cdclk(dev_priv, cdclk_state);
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dev_priv->display.set_cdclk(dev_priv, cdclk_state, pipe);
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if (WARN(intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state),
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"cdclk state doesn't match!\n")) {
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@ -2158,6 +2197,46 @@ void intel_set_cdclk(struct drm_i915_private *dev_priv,
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}
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}
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/**
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* intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware
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* @dev_priv: i915 device
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* @old_state: old CDCLK state
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* @new_state: new CDCLK state
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* @pipe: pipe with which to synchronize the update
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*
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* Program the hardware before updating the HW plane state based on the passed
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* in CDCLK state, if necessary.
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*/
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void
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intel_set_cdclk_pre_plane_update(struct drm_i915_private *dev_priv,
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const struct intel_cdclk_state *old_state,
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const struct intel_cdclk_state *new_state,
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enum pipe pipe)
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{
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if (pipe == INVALID_PIPE || old_state->cdclk <= new_state->cdclk)
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intel_set_cdclk(dev_priv, new_state, pipe);
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}
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/**
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* intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware
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* @dev_priv: i915 device
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* @old_state: old CDCLK state
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* @new_state: new CDCLK state
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* @pipe: pipe with which to synchronize the update
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*
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* Program the hardware after updating the HW plane state based on the passed
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* in CDCLK state, if necessary.
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*/
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void
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intel_set_cdclk_post_plane_update(struct drm_i915_private *dev_priv,
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const struct intel_cdclk_state *old_state,
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const struct intel_cdclk_state *new_state,
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enum pipe pipe)
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{
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if (pipe != INVALID_PIPE && old_state->cdclk > new_state->cdclk)
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intel_set_cdclk(dev_priv, new_state, pipe);
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}
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static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv,
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int pixel_rate)
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{
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@ -13002,6 +13002,7 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
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intel_state->active_crtcs = dev_priv->active_crtcs;
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intel_state->cdclk.logical = dev_priv->cdclk.logical;
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intel_state->cdclk.actual = dev_priv->cdclk.actual;
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intel_state->cdclk.pipe = INVALID_PIPE;
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for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
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if (new_crtc_state->active)
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@ -13021,6 +13022,8 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
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* adjusted_mode bits in the crtc directly.
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*/
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if (dev_priv->display.modeset_calc_cdclk) {
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enum pipe pipe;
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ret = dev_priv->display.modeset_calc_cdclk(state);
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if (ret < 0)
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return ret;
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@ -13037,12 +13040,36 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
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return ret;
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}
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if (is_power_of_2(intel_state->active_crtcs)) {
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struct drm_crtc *crtc;
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struct drm_crtc_state *crtc_state;
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pipe = ilog2(intel_state->active_crtcs);
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crtc = &intel_get_crtc_for_pipe(dev_priv, pipe)->base;
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crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
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if (crtc_state && needs_modeset(crtc_state))
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pipe = INVALID_PIPE;
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} else {
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pipe = INVALID_PIPE;
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}
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/* All pipes must be switched off while we change the cdclk. */
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if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual,
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&intel_state->cdclk.actual)) {
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if (pipe != INVALID_PIPE &&
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intel_cdclk_needs_cd2x_update(dev_priv,
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&dev_priv->cdclk.actual,
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&intel_state->cdclk.actual)) {
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ret = intel_lock_all_pipes(state);
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if (ret < 0)
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return ret;
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intel_state->cdclk.pipe = pipe;
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} else if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual,
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&intel_state->cdclk.actual)) {
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ret = intel_modeset_all_pipes(state);
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if (ret < 0)
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return ret;
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intel_state->cdclk.pipe = INVALID_PIPE;
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}
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DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
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@ -13451,7 +13478,10 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
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|||
if (intel_state->modeset) {
|
||||
drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
|
||||
|
||||
intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
|
||||
intel_set_cdclk_pre_plane_update(dev_priv,
|
||||
&intel_state->cdclk.actual,
|
||||
&dev_priv->cdclk.actual,
|
||||
intel_state->cdclk.pipe);
|
||||
|
||||
/*
|
||||
* SKL workaround: bspec recommends we disable the SAGV when we
|
||||
|
|
@ -13480,6 +13510,12 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
|
|||
/* Now enable the clocks, plane, pipe, and connectors that we set up. */
|
||||
dev_priv->display.update_crtcs(state);
|
||||
|
||||
if (intel_state->modeset)
|
||||
intel_set_cdclk_post_plane_update(dev_priv,
|
||||
&intel_state->cdclk.actual,
|
||||
&dev_priv->cdclk.actual,
|
||||
intel_state->cdclk.pipe);
|
||||
|
||||
/* FIXME: We should call drm_atomic_helper_commit_hw_done() here
|
||||
* already, but still need the state for the delayed optimization. To
|
||||
* fix this:
|
||||
|
|
|
|||
|
|
@ -559,6 +559,8 @@ struct intel_atomic_state {
|
|||
|
||||
int force_min_cdclk;
|
||||
bool force_min_cdclk_changed;
|
||||
/* pipe to which cd2x update is synchronized */
|
||||
enum pipe pipe;
|
||||
} cdclk;
|
||||
|
||||
bool dpll_set, modeset;
|
||||
|
|
@ -1694,13 +1696,24 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
|
|||
void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
|
||||
void intel_update_cdclk(struct drm_i915_private *dev_priv);
|
||||
void intel_update_rawclk(struct drm_i915_private *dev_priv);
|
||||
bool intel_cdclk_needs_cd2x_update(struct drm_i915_private *dev_priv,
|
||||
const struct intel_cdclk_state *a,
|
||||
const struct intel_cdclk_state *b);
|
||||
bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
|
||||
const struct intel_cdclk_state *b);
|
||||
bool intel_cdclk_changed(const struct intel_cdclk_state *a,
|
||||
const struct intel_cdclk_state *b);
|
||||
void intel_cdclk_swap_state(struct intel_atomic_state *state);
|
||||
void intel_set_cdclk(struct drm_i915_private *dev_priv,
|
||||
const struct intel_cdclk_state *cdclk_state);
|
||||
void
|
||||
intel_set_cdclk_pre_plane_update(struct drm_i915_private *dev_priv,
|
||||
const struct intel_cdclk_state *old_state,
|
||||
const struct intel_cdclk_state *new_state,
|
||||
enum pipe pipe);
|
||||
void
|
||||
intel_set_cdclk_post_plane_update(struct drm_i915_private *dev_priv,
|
||||
const struct intel_cdclk_state *old_state,
|
||||
const struct intel_cdclk_state *new_state,
|
||||
enum pipe pipe);
|
||||
void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
|
||||
const char *context);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue