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drm/amd/display: clean up dcn soc params 

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dmytro Laktyushkin 2017-11-28 11:22:15 -05:00 committed by Alex Deucher
parent 58fc625b5e
commit 5a095c405e
3 changed files with 0 additions and 62 deletions
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29
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
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@ -1585,35 +1585,6 @@ void dcn_bw_sync_calcs_and_dml(struct dc *dc)
dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one,
dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed,
dc->dcn_ip->dcfclk_cstate_latency);
dc->dml.soc.vmin.socclk_mhz = dc->dcn_soc->socclk;
dc->dml.soc.vmid.socclk_mhz = dc->dcn_soc->socclk;
dc->dml.soc.vnom.socclk_mhz = dc->dcn_soc->socclk;
dc->dml.soc.vmax.socclk_mhz = dc->dcn_soc->socclk;
dc->dml.soc.vmin.dcfclk_mhz = dc->dcn_soc->dcfclkv_min0p65;
dc->dml.soc.vmid.dcfclk_mhz = dc->dcn_soc->dcfclkv_mid0p72;
dc->dml.soc.vnom.dcfclk_mhz = dc->dcn_soc->dcfclkv_nom0p8;
dc->dml.soc.vmax.dcfclk_mhz = dc->dcn_soc->dcfclkv_max0p9;
dc->dml.soc.vmin.dispclk_mhz = dc->dcn_soc->max_dispclk_vmin0p65;
dc->dml.soc.vmid.dispclk_mhz = dc->dcn_soc->max_dispclk_vmid0p72;
dc->dml.soc.vnom.dispclk_mhz = dc->dcn_soc->max_dispclk_vnom0p8;
dc->dml.soc.vmax.dispclk_mhz = dc->dcn_soc->max_dispclk_vmax0p9;
dc->dml.soc.vmin.dppclk_mhz = dc->dcn_soc->max_dppclk_vmin0p65;
dc->dml.soc.vmid.dppclk_mhz = dc->dcn_soc->max_dppclk_vmid0p72;
dc->dml.soc.vnom.dppclk_mhz = dc->dcn_soc->max_dppclk_vnom0p8;
dc->dml.soc.vmax.dppclk_mhz = dc->dcn_soc->max_dppclk_vmax0p9;
dc->dml.soc.vmin.phyclk_mhz = dc->dcn_soc->phyclkv_min0p65;
dc->dml.soc.vmid.phyclk_mhz = dc->dcn_soc->phyclkv_mid0p72;
dc->dml.soc.vnom.phyclk_mhz = dc->dcn_soc->phyclkv_nom0p8;
dc->dml.soc.vmax.phyclk_mhz = dc->dcn_soc->phyclkv_max0p9;
dc->dml.soc.vmin.dram_bw_per_chan_gbps = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65;
dc->dml.soc.vmid.dram_bw_per_chan_gbps = dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72;
dc->dml.soc.vnom.dram_bw_per_chan_gbps = dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8;
dc->dml.soc.vmax.dram_bw_per_chan_gbps = dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9;
dc->dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time;
dc->dml.soc.sr_enter_plus_exit_time_us = dc->dcn_soc->sr_enter_plus_exit_time;

29
drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
View File

@ -35,35 +35,6 @@ static void set_soc_bounding_box(struct _vcs_dpi_soc_bounding_box_st *soc, enum
soc->writeback_latency_us = 12.0;
soc->ideal_dram_bw_after_urgent_percent = 80.0;
soc->max_request_size_bytes = 256;
soc->vmin.dcfclk_mhz = 300.0;
soc->vmin.dispclk_mhz = 608.0;
soc->vmin.dppclk_mhz = 435.0;
soc->vmin.dram_bw_per_chan_gbps = 12.8;
soc->vmin.phyclk_mhz = 540.0;
soc->vmin.socclk_mhz = 208.0;
soc->vmid.dcfclk_mhz = 600.0;
soc->vmid.dispclk_mhz = 661.0;
soc->vmid.dppclk_mhz = 661.0;
soc->vmid.dram_bw_per_chan_gbps = 12.8;
soc->vmid.phyclk_mhz = 540.0;
soc->vmid.socclk_mhz = 208.0;
soc->vnom.dcfclk_mhz = 600.0;
soc->vnom.dispclk_mhz = 661.0;
soc->vnom.dppclk_mhz = 661.0;
soc->vnom.dram_bw_per_chan_gbps = 38.4;
soc->vnom.phyclk_mhz = 810;
soc->vnom.socclk_mhz = 208.0;
soc->vmax.dcfclk_mhz = 600.0;
soc->vmax.dispclk_mhz = 1086.0;
soc->vmax.dppclk_mhz = 661.0;
soc->vmax.dram_bw_per_chan_gbps = 38.4;
soc->vmax.phyclk_mhz = 810.0;
soc->vmax.socclk_mhz = 208.0;
soc->downspread_percent = 0.5;
soc->dram_page_open_time_ns = 50.0;
soc->dram_rw_turnaround_time_ns = 17.5;

4
drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
View File

@ -79,10 +79,6 @@ struct _vcs_dpi_soc_bounding_box_st {
double writeback_latency_us;
double ideal_dram_bw_after_urgent_percent;
unsigned int max_request_size_bytes;
struct _vcs_dpi_voltage_scaling_st vmin;
struct _vcs_dpi_voltage_scaling_st vmid;
struct _vcs_dpi_voltage_scaling_st vnom;
struct _vcs_dpi_voltage_scaling_st vmax;
double downspread_percent;
double dram_page_open_time_ns;
double dram_rw_turnaround_time_ns;