x86/process: Optimize TIF_NOTSC switch
Provide and use a toggle helper instead of doing it with a branch. x86_64: arch/x86/kernel/process.o text data bss dec hex 3008 8577 16 11601 2d51 Before 2976 8577 16 11569 2d31 After i386: arch/x86/kernel/process.o text data bss dec hex 2925 8673 8 11606 2d56 Before 2893 8673 8 11574 2d36 After Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Andy Lutomirski <luto@kernel.org> Link: http://lkml.kernel.org/r/20170214081104.9244-4-khuey@kylehuey.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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@ -110,6 +110,16 @@ static inline void cr4_clear_bits(unsigned long mask)
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}
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}
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static inline void cr4_toggle_bits(unsigned long mask)
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{
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unsigned long cr4;
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cr4 = this_cpu_read(cpu_tlbstate.cr4);
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cr4 ^= mask;
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this_cpu_write(cpu_tlbstate.cr4, cr4);
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__write_cr4(cr4);
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}
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/* Read the CR4 shadow. */
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static inline unsigned long cr4_read_shadow(void)
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{
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@ -124,11 +124,6 @@ void flush_thread(void)
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fpu__clear(&tsk->thread.fpu);
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}
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static void hard_disable_TSC(void)
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{
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cr4_set_bits(X86_CR4_TSD);
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}
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void disable_TSC(void)
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{
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preempt_disable();
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@ -137,15 +132,10 @@ void disable_TSC(void)
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* Must flip the CPU state synchronously with
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* TIF_NOTSC in the current running context.
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*/
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hard_disable_TSC();
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cr4_set_bits(X86_CR4_TSD);
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preempt_enable();
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}
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static void hard_enable_TSC(void)
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{
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cr4_clear_bits(X86_CR4_TSD);
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}
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static void enable_TSC(void)
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{
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preempt_disable();
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@ -154,7 +144,7 @@ static void enable_TSC(void)
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* Must flip the CPU state synchronously with
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* TIF_NOTSC in the current running context.
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*/
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hard_enable_TSC();
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cr4_clear_bits(X86_CR4_TSD);
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preempt_enable();
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}
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@ -233,12 +223,8 @@ void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
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wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
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}
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if ((tifp ^ tifn) & _TIF_NOTSC) {
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if (tifn & _TIF_NOTSC)
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hard_disable_TSC();
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else
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hard_enable_TSC();
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}
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if ((tifp ^ tifn) & _TIF_NOTSC)
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cr4_toggle_bits(X86_CR4_TSD);
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}
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/*
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