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drm/nouveau/i2c: cosmetic changes 

This is purely preparation for upcoming commits, there should be no
code changes here.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2015-08-20 14:54:06 +10:00
parent e7d6518104
commit 5b920d9264
9 changed files with 38 additions and 50 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h
View File

@ -59,7 +59,7 @@ struct nvkm_i2c_board_info {
};
struct nvkm_i2c {
struct nvkm_subdev base;
struct nvkm_subdev subdev;
struct nvkm_event event;
struct nvkm_i2c_port *(*find)(struct nvkm_i2c *, u8 index);

6
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c
View File

@ -413,7 +413,7 @@ _nvkm_i2c_fini(struct nvkm_object *object, bool suspend)
impl->aux_stat(i2c, &mask, &mask, &mask, &mask);
}
return nvkm_subdev_fini(&i2c->base, suspend);
return nvkm_subdev_fini(&i2c->subdev, suspend);
fail:
list_for_each_entry_continue_reverse(port, &i2c->ports, head) {
nv_ofuncs(port)->init(nv_object(port));
@ -429,7 +429,7 @@ _nvkm_i2c_init(struct nvkm_object *object)
struct nvkm_i2c_port *port;
int ret;
ret = nvkm_subdev_init(&i2c->base);
ret = nvkm_subdev_init(&i2c->subdev);
if (ret == 0) {
list_for_each_entry(port, &i2c->ports, head) {
ret = nv_ofuncs(port)->init(nv_object(port));
@ -459,7 +459,7 @@ _nvkm_i2c_dtor(struct nvkm_object *object)
nvkm_object_ref(NULL, (struct nvkm_object **)&port);
}
nvkm_subdev_destroy(&i2c->base);
nvkm_subdev_destroy(&i2c->subdev);
}
static struct nvkm_oclass *

2
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/g94.c
View File

@ -111,7 +111,7 @@ g94_aux(struct nvkm_i2c_port *base, bool retry,
AUX_DBG("%d: 0x%08x %d\n", type, addr, size);
ret = auxch_init(aux, ch);
if (ret)
if (ret < 0)
goto out;
stat = nv_rd32(aux, 0x00e4e8 + (ch * 0x50));

8
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf110.c
View File

@ -26,17 +26,17 @@
static int
gf110_i2c_sense_scl(struct nvkm_i2c_port *base)
{
struct nv50_i2c_priv *priv = (void *)nvkm_i2c(base);
struct nvkm_i2c *i2c = (void *)nvkm_i2c(base);
struct nv50_i2c_port *port = (void *)base;
return !!(nv_rd32(priv, port->addr) & 0x00000010);
return !!(nv_rd32(i2c, port->addr) & 0x00000010);
}
static int
gf110_i2c_sense_sda(struct nvkm_i2c_port *base)
{
struct nv50_i2c_priv *priv = (void *)nvkm_i2c(base);
struct nvkm_i2c *i2c = (void *)nvkm_i2c(base);
struct nv50_i2c_port *port = (void *)base;
return !!(nv_rd32(priv, port->addr) & 0x00000020);
return !!(nv_rd32(i2c, port->addr) & 0x00000020);
}
static const struct nvkm_i2c_func

2
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gm204.c
View File

@ -81,7 +81,7 @@ gm204_aux(struct nvkm_i2c_port *base, bool retry,
AUX_DBG("%d: 0x%08x %d\n", type, addr, size);
ret = auxch_init(aux, ch);
if (ret)
if (ret < 0)
goto out;
stat = nv_rd32(aux, 0x00d958 + (ch * 0x50));

24
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv04.c
View File

@ -25,10 +25,6 @@
#include <subdev/vga.h>
struct nv04_i2c_priv {
struct nvkm_i2c base;
};
struct nv04_i2c_port {
struct nvkm_i2c_port base;
u8 drive;
@ -38,39 +34,39 @@ struct nv04_i2c_port {
static void
nv04_i2c_drive_scl(struct nvkm_i2c_port *base, int state)
{
struct nv04_i2c_priv *priv = (void *)nvkm_i2c(base);
struct nvkm_i2c *i2c = (void *)nvkm_i2c(base);
struct nv04_i2c_port *port = (void *)base;
u8 val = nv_rdvgac(priv, 0, port->drive);
u8 val = nv_rdvgac(i2c, 0, port->drive);
if (state) val |= 0x20;
else val &= 0xdf;
nv_wrvgac(priv, 0, port->drive, val | 0x01);
nv_wrvgac(i2c, 0, port->drive, val | 0x01);
}
static void
nv04_i2c_drive_sda(struct nvkm_i2c_port *base, int state)
{
struct nv04_i2c_priv *priv = (void *)nvkm_i2c(base);
struct nvkm_i2c *i2c = (void *)nvkm_i2c(base);
struct nv04_i2c_port *port = (void *)base;
u8 val = nv_rdvgac(priv, 0, port->drive);
u8 val = nv_rdvgac(i2c, 0, port->drive);
if (state) val |= 0x10;
else val &= 0xef;
nv_wrvgac(priv, 0, port->drive, val | 0x01);
nv_wrvgac(i2c, 0, port->drive, val | 0x01);
}
static int
nv04_i2c_sense_scl(struct nvkm_i2c_port *base)
{
struct nv04_i2c_priv *priv = (void *)nvkm_i2c(base);
struct nvkm_i2c *i2c = (void *)nvkm_i2c(base);
struct nv04_i2c_port *port = (void *)base;
return !!(nv_rdvgac(priv, 0, port->sense) & 0x04);
return !!(nv_rdvgac(i2c, 0, port->sense) & 0x04);
}
static int
nv04_i2c_sense_sda(struct nvkm_i2c_port *base)
{
struct nv04_i2c_priv *priv = (void *)nvkm_i2c(base);
struct nvkm_i2c *i2c = (void *)nvkm_i2c(base);
struct nv04_i2c_port *port = (void *)base;
return !!(nv_rdvgac(priv, 0, port->sense) & 0x08);
return !!(nv_rdvgac(i2c, 0, port->sense) & 0x08);
}
static const struct nvkm_i2c_func

20
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv4e.c
View File

@ -25,10 +25,6 @@
#include <subdev/vga.h>
struct nv4e_i2c_priv {
struct nvkm_i2c base;
};
struct nv4e_i2c_port {
struct nvkm_i2c_port base;
u32 addr;
@ -37,33 +33,33 @@ struct nv4e_i2c_port {
static void
nv4e_i2c_drive_scl(struct nvkm_i2c_port *base, int state)
{
struct nv4e_i2c_priv *priv = (void *)nvkm_i2c(base);
struct nvkm_i2c *i2c = (void *)nvkm_i2c(base);
struct nv4e_i2c_port *port = (void *)base;
nv_mask(priv, port->addr, 0x2f, state ? 0x21 : 0x01);
nv_mask(i2c, port->addr, 0x2f, state ? 0x21 : 0x01);
}
static void
nv4e_i2c_drive_sda(struct nvkm_i2c_port *base, int state)
{
struct nv4e_i2c_priv *priv = (void *)nvkm_i2c(base);
struct nvkm_i2c *i2c = (void *)nvkm_i2c(base);
struct nv4e_i2c_port *port = (void *)base;
nv_mask(priv, port->addr, 0x1f, state ? 0x11 : 0x01);
nv_mask(i2c, port->addr, 0x1f, state ? 0x11 : 0x01);
}
static int
nv4e_i2c_sense_scl(struct nvkm_i2c_port *base)
{
struct nv4e_i2c_priv *priv = (void *)nvkm_i2c(base);
struct nvkm_i2c *i2c = (void *)nvkm_i2c(base);
struct nv4e_i2c_port *port = (void *)base;
return !!(nv_rd32(priv, port->addr) & 0x00040000);
return !!(nv_rd32(i2c, port->addr) & 0x00040000);
}
static int
nv4e_i2c_sense_sda(struct nvkm_i2c_port *base)
{
struct nv4e_i2c_priv *priv = (void *)nvkm_i2c(base);
struct nvkm_i2c *i2c = (void *)nvkm_i2c(base);
struct nv4e_i2c_port *port = (void *)base;
return !!(nv_rd32(priv, port->addr) & 0x00080000);
return !!(nv_rd32(i2c, port->addr) & 0x00080000);
}
static const struct nvkm_i2c_func

20
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv50.c
View File

@ -26,37 +26,37 @@
void
nv50_i2c_drive_scl(struct nvkm_i2c_port *base, int state)
{
struct nv50_i2c_priv *priv = (void *)nvkm_i2c(base);
struct nvkm_i2c *i2c = (void *)nvkm_i2c(base);
struct nv50_i2c_port *port = (void *)base;
if (state) port->state |= 0x01;
else port->state &= 0xfe;
nv_wr32(priv, port->addr, port->state);
nv_wr32(i2c, port->addr, port->state);
}
void
nv50_i2c_drive_sda(struct nvkm_i2c_port *base, int state)
{
struct nv50_i2c_priv *priv = (void *)nvkm_i2c(base);
struct nvkm_i2c *i2c = (void *)nvkm_i2c(base);
struct nv50_i2c_port *port = (void *)base;
if (state) port->state |= 0x02;
else port->state &= 0xfd;
nv_wr32(priv, port->addr, port->state);
nv_wr32(i2c, port->addr, port->state);
}
int
nv50_i2c_sense_scl(struct nvkm_i2c_port *base)
{
struct nv50_i2c_priv *priv = (void *)nvkm_i2c(base);
struct nvkm_i2c *i2c = (void *)nvkm_i2c(base);
struct nv50_i2c_port *port = (void *)base;
return !!(nv_rd32(priv, port->addr) & 0x00000001);
return !!(nv_rd32(i2c, port->addr) & 0x00000001);
}
int
nv50_i2c_sense_sda(struct nvkm_i2c_port *base)
{
struct nv50_i2c_priv *priv = (void *)nvkm_i2c(base);
struct nvkm_i2c *i2c = (void *)nvkm_i2c(base);
struct nv50_i2c_port *port = (void *)base;
return !!(nv_rd32(priv, port->addr) & 0x00000002);
return !!(nv_rd32(i2c, port->addr) & 0x00000002);
}
static const struct nvkm_i2c_func
@ -100,9 +100,9 @@ nv50_i2c_port_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
int
nv50_i2c_port_init(struct nvkm_object *object)
{
struct nv50_i2c_priv *priv = (void *)nvkm_i2c(object);
struct nvkm_i2c *i2c = (void *)nvkm_i2c(object);
struct nv50_i2c_port *port = (void *)object;
nv_wr32(priv, port->addr, port->state);
nv_wr32(i2c, port->addr, port->state);
return nvkm_i2c_port_init(&port->base);
}

4
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv50.h
View File

@ -2,10 +2,6 @@
#define __NV50_I2C_H__
#include "priv.h"
struct nv50_i2c_priv {
struct nvkm_i2c base;
};
struct nv50_i2c_port {
struct nvkm_i2c_port base;
u32 addr;