pinctrl: zynq: fix offset address for {SD0,SD1}_WP_CD_SEL
The address for SD0_WP_CD_SEL, SD1_WP_CD_SEL is 0xf8000830,
0xf8000834, respectively.
Each offset address must be prefixed with 0x.
Fixes: add958cee9
"pinctrl: Add driver for Zynq"
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
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@ -801,15 +801,15 @@ static const struct zynq_pinmux_function zynq_pmux_functions[] = {
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DEFINE_ZYNQ_PINMUX_FUNCTION(spi1_ss, 0x50),
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DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0, 0x40),
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DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0_pc, 0xc),
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DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_wp, 0, 130, ZYNQ_SDIO_WP_MASK,
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DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_wp, 0, 0x130, ZYNQ_SDIO_WP_MASK,
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ZYNQ_SDIO_WP_SHIFT),
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DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_cd, 0, 130, ZYNQ_SDIO_CD_MASK,
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DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_cd, 0, 0x130, ZYNQ_SDIO_CD_MASK,
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ZYNQ_SDIO_CD_SHIFT),
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DEFINE_ZYNQ_PINMUX_FUNCTION(sdio1, 0x40),
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DEFINE_ZYNQ_PINMUX_FUNCTION(sdio1_pc, 0xc),
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DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_wp, 0, 134, ZYNQ_SDIO_WP_MASK,
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DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_wp, 0, 0x134, ZYNQ_SDIO_WP_MASK,
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ZYNQ_SDIO_WP_SHIFT),
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DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_cd, 0, 134, ZYNQ_SDIO_CD_MASK,
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DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_cd, 0, 0x134, ZYNQ_SDIO_CD_MASK,
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ZYNQ_SDIO_CD_SHIFT),
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DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor, 4),
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DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor_cs1, 8),
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