clocksource/drivers/rockchip_timer: Implement clocksource timer
The clock supplying the arm-global-timer on the rk3188 is coming from the
the cpu clock itself and thus changes its rate everytime cpufreq adjusts
the cpu frequency making this timer unsuitable as a stable clocksource
and sched clock.
The rk3188, rk3288 and following socs share a separate timer block already
handled by the rockchip-timer driver. Therefore adapt this driver to also
be able to act as clocksource and sched clock on rk3188.
In order to test clocksource you can run following commands and check
how much time it take in real. On rk3188 it take about ~45 seconds.
cpufreq-set -f 1.6GHZ
date; sleep 60; date
In order to use the patch you need to declare two timers in the dts
file. The first timer will be initialized as clockevent provider
and the second one as clocksource. The clockevent must be from
alive subsystem as it used as backup for the local timers at sleep
time.
The patch does not break compatibility with older device tree files.
The older device tree files contain only one timer. The timer
will be initialized as clockevent, as expected.
rk3288 (and probably anything newer) is irrelevant to this patch,
as it has the arch timer interface. This patch may be useful
for Cortex-A9/A5 based parts.
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
This commit is contained in:
Alexander Kochetkov
Daniel Lezcano
parent
b72af3462d
commit
5e0a39d0f7
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@ -81,6 +81,7 @@ config ROCKCHIP_TIMER
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bool "Rockchip timer driver" if COMPILE_TEST
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depends on ARM || ARM64
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select CLKSRC_OF
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select CLKSRC_MMIO
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help
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Enables the support for the rockchip timer driver.
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@ -11,6 +11,8 @@
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#include <linux/clockchips.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/sched_clock.h>
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#include <linux/slab.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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@ -19,6 +21,8 @@
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#define TIMER_LOAD_COUNT0 0x00
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#define TIMER_LOAD_COUNT1 0x04
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#define TIMER_CURRENT_VALUE0 0x08
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#define TIMER_CURRENT_VALUE1 0x0C
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#define TIMER_CONTROL_REG3288 0x10
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#define TIMER_CONTROL_REG3399 0x1c
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#define TIMER_INT_STATUS 0x18
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@ -29,103 +33,118 @@
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#define TIMER_MODE_USER_DEFINED_COUNT (1 << 1)
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#define TIMER_INT_UNMASK (1 << 2)
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struct bc_timer {
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struct clock_event_device ce;
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struct rk_timer {
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void __iomem *base;
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void __iomem *ctrl;
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struct clk *clk;
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struct clk *pclk;
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u32 freq;
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int irq;
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};
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static struct bc_timer bc_timer;
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struct rk_clkevt {
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struct clock_event_device ce;
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struct rk_timer timer;
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};
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static inline struct bc_timer *rk_timer(struct clock_event_device *ce)
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static struct rk_clkevt *rk_clkevt;
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static struct rk_timer *rk_clksrc;
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static inline struct rk_timer *rk_timer(struct clock_event_device *ce)
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{
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return container_of(ce, struct bc_timer, ce);
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return &container_of(ce, struct rk_clkevt, ce)->timer;
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}
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static inline void __iomem *rk_base(struct clock_event_device *ce)
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static inline void rk_timer_disable(struct rk_timer *timer)
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{
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return rk_timer(ce)->base;
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writel_relaxed(TIMER_DISABLE, timer->ctrl);
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}
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static inline void __iomem *rk_ctrl(struct clock_event_device *ce)
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static inline void rk_timer_enable(struct rk_timer *timer, u32 flags)
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{
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return rk_timer(ce)->ctrl;
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}
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static inline void rk_timer_disable(struct clock_event_device *ce)
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{
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writel_relaxed(TIMER_DISABLE, rk_ctrl(ce));
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}
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static inline void rk_timer_enable(struct clock_event_device *ce, u32 flags)
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{
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writel_relaxed(TIMER_ENABLE | TIMER_INT_UNMASK | flags,
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rk_ctrl(ce));
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writel_relaxed(TIMER_ENABLE | flags, timer->ctrl);
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}
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static void rk_timer_update_counter(unsigned long cycles,
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struct clock_event_device *ce)
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struct rk_timer *timer)
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{
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writel_relaxed(cycles, rk_base(ce) + TIMER_LOAD_COUNT0);
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writel_relaxed(0, rk_base(ce) + TIMER_LOAD_COUNT1);
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writel_relaxed(cycles, timer->base + TIMER_LOAD_COUNT0);
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writel_relaxed(0, timer->base + TIMER_LOAD_COUNT1);
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}
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static void rk_timer_interrupt_clear(struct clock_event_device *ce)
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static void rk_timer_interrupt_clear(struct rk_timer *timer)
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{
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writel_relaxed(1, rk_base(ce) + TIMER_INT_STATUS);
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writel_relaxed(1, timer->base + TIMER_INT_STATUS);
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}
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static inline int rk_timer_set_next_event(unsigned long cycles,
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struct clock_event_device *ce)
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{
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rk_timer_disable(ce);
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rk_timer_update_counter(cycles, ce);
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rk_timer_enable(ce, TIMER_MODE_USER_DEFINED_COUNT);
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struct rk_timer *timer = rk_timer(ce);
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rk_timer_disable(timer);
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rk_timer_update_counter(cycles, timer);
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rk_timer_enable(timer, TIMER_MODE_USER_DEFINED_COUNT |
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TIMER_INT_UNMASK);
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return 0;
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}
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static int rk_timer_shutdown(struct clock_event_device *ce)
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{
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rk_timer_disable(ce);
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struct rk_timer *timer = rk_timer(ce);
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rk_timer_disable(timer);
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return 0;
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}
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static int rk_timer_set_periodic(struct clock_event_device *ce)
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{
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rk_timer_disable(ce);
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rk_timer_update_counter(rk_timer(ce)->freq / HZ - 1, ce);
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rk_timer_enable(ce, TIMER_MODE_FREE_RUNNING);
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struct rk_timer *timer = rk_timer(ce);
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rk_timer_disable(timer);
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rk_timer_update_counter(timer->freq / HZ - 1, timer);
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rk_timer_enable(timer, TIMER_MODE_FREE_RUNNING | TIMER_INT_UNMASK);
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return 0;
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}
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static irqreturn_t rk_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *ce = dev_id;
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struct rk_timer *timer = rk_timer(ce);
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rk_timer_interrupt_clear(ce);
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rk_timer_interrupt_clear(timer);
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if (clockevent_state_oneshot(ce))
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rk_timer_disable(ce);
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rk_timer_disable(timer);
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ce->event_handler(ce);
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return IRQ_HANDLED;
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}
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static int __init rk_timer_init(struct device_node *np, u32 ctrl_reg)
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static u64 notrace rk_timer_sched_read(void)
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{
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return ~readl_relaxed(rk_clksrc->base + TIMER_CURRENT_VALUE0);
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}
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static int __init
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rk_timer_probe(struct rk_timer *timer, struct device_node *np)
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{
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struct clock_event_device *ce = &bc_timer.ce;
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struct clk *timer_clk;
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struct clk *pclk;
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int ret = -EINVAL, irq;
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u32 ctrl_reg = TIMER_CONTROL_REG3288;
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bc_timer.base = of_iomap(np, 0);
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if (!bc_timer.base) {
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timer->base = of_iomap(np, 0);
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if (!timer->base) {
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pr_err("Failed to get base address for '%s'\n", TIMER_NAME);
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return -ENXIO;
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}
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bc_timer.ctrl = bc_timer.base + ctrl_reg;
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if (of_device_is_compatible(np, "rockchip,rk3399-timer"))
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ctrl_reg = TIMER_CONTROL_REG3399;
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timer->ctrl = timer->base + ctrl_reg;
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pclk = of_clk_get_by_name(np, "pclk");
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if (IS_ERR(pclk)) {
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@ -139,6 +158,7 @@ static int __init rk_timer_init(struct device_node *np, u32 ctrl_reg)
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pr_err("Failed to enable pclk for '%s'\n", TIMER_NAME);
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goto out_unmap;
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}
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timer->pclk = pclk;
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timer_clk = of_clk_get_by_name(np, "timer");
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if (IS_ERR(timer_clk)) {
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@ -152,8 +172,9 @@ static int __init rk_timer_init(struct device_node *np, u32 ctrl_reg)
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pr_err("Failed to enable timer clock\n");
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goto out_timer_clk;
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}
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timer->clk = timer_clk;
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bc_timer.freq = clk_get_rate(timer_clk);
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timer->freq = clk_get_rate(timer_clk);
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irq = irq_of_parse_and_map(np, 0);
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if (!irq) {
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@ -161,28 +182,10 @@ static int __init rk_timer_init(struct device_node *np, u32 ctrl_reg)
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pr_err("Failed to map interrupts for '%s'\n", TIMER_NAME);
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goto out_irq;
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}
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timer->irq = irq;
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ce->name = TIMER_NAME;
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ce->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
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CLOCK_EVT_FEAT_DYNIRQ;
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ce->set_next_event = rk_timer_set_next_event;
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ce->set_state_shutdown = rk_timer_shutdown;
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ce->set_state_periodic = rk_timer_set_periodic;
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ce->irq = irq;
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ce->cpumask = cpu_possible_mask;
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ce->rating = 250;
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rk_timer_interrupt_clear(ce);
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rk_timer_disable(ce);
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ret = request_irq(irq, rk_timer_interrupt, IRQF_TIMER, TIMER_NAME, ce);
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if (ret) {
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pr_err("Failed to initialize '%s': %d\n", TIMER_NAME, ret);
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goto out_irq;
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}
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clockevents_config_and_register(ce, bc_timer.freq, 1, UINT_MAX);
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rk_timer_interrupt_clear(timer);
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rk_timer_disable(timer);
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return 0;
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out_irq:
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@ -190,22 +193,115 @@ static int __init rk_timer_init(struct device_node *np, u32 ctrl_reg)
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out_timer_clk:
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clk_disable_unprepare(pclk);
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out_unmap:
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iounmap(bc_timer.base);
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iounmap(timer->base);
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return ret;
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}
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static int __init rk3288_timer_init(struct device_node *np)
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static void __init rk_timer_cleanup(struct rk_timer *timer)
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{
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return rk_timer_init(np, TIMER_CONTROL_REG3288);
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clk_disable_unprepare(timer->clk);
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clk_disable_unprepare(timer->pclk);
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iounmap(timer->base);
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}
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static int __init rk3399_timer_init(struct device_node *np)
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static int __init rk_clkevt_init(struct device_node *np)
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{
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return rk_timer_init(np, TIMER_CONTROL_REG3399);
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struct clock_event_device *ce;
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int ret = -EINVAL;
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rk_clkevt = kzalloc(sizeof(struct rk_clkevt), GFP_KERNEL);
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if (!rk_clkevt) {
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ret = -ENOMEM;
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goto out;
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}
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ret = rk_timer_probe(&rk_clkevt->timer, np);
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if (ret)
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goto out_probe;
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ce = &rk_clkevt->ce;
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ce->name = TIMER_NAME;
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ce->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
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CLOCK_EVT_FEAT_DYNIRQ;
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ce->set_next_event = rk_timer_set_next_event;
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ce->set_state_shutdown = rk_timer_shutdown;
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ce->set_state_periodic = rk_timer_set_periodic;
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ce->irq = rk_clkevt->timer.irq;
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ce->cpumask = cpu_possible_mask;
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ce->rating = 250;
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ret = request_irq(rk_clkevt->timer.irq, rk_timer_interrupt, IRQF_TIMER,
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TIMER_NAME, ce);
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if (ret) {
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pr_err("Failed to initialize '%s': %d\n",
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TIMER_NAME, ret);
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goto out_irq;
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}
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clockevents_config_and_register(&rk_clkevt->ce,
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rk_clkevt->timer.freq, 1, UINT_MAX);
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return 0;
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out_irq:
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rk_timer_cleanup(&rk_clkevt->timer);
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out_probe:
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kfree(rk_clkevt);
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out:
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/* Leave rk_clkevt not NULL to prevent future init */
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rk_clkevt = ERR_PTR(ret);
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return ret;
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}
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CLOCKSOURCE_OF_DECLARE(rk3288_timer, "rockchip,rk3288-timer",
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rk3288_timer_init);
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CLOCKSOURCE_OF_DECLARE(rk3399_timer, "rockchip,rk3399-timer",
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rk3399_timer_init);
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static int __init rk_clksrc_init(struct device_node *np)
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{
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int ret = -EINVAL;
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rk_clksrc = kzalloc(sizeof(struct rk_timer), GFP_KERNEL);
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if (!rk_clksrc) {
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ret = -ENOMEM;
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goto out;
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}
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ret = rk_timer_probe(rk_clksrc, np);
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if (ret)
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goto out_probe;
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rk_timer_update_counter(UINT_MAX, rk_clksrc);
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rk_timer_enable(rk_clksrc, 0);
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ret = clocksource_mmio_init(rk_clksrc->base + TIMER_CURRENT_VALUE0,
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TIMER_NAME, rk_clksrc->freq, 250, 32,
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clocksource_mmio_readl_down);
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if (ret) {
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pr_err("Failed to register clocksource");
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goto out_clocksource;
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}
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sched_clock_register(rk_timer_sched_read, 32, rk_clksrc->freq);
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return 0;
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out_clocksource:
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rk_timer_cleanup(rk_clksrc);
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out_probe:
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kfree(rk_clksrc);
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out:
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/* Leave rk_clksrc not NULL to prevent future init */
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rk_clksrc = ERR_PTR(ret);
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return ret;
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}
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static int __init rk_timer_init(struct device_node *np)
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{
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if (!rk_clkevt)
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return rk_clkevt_init(np);
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if (!rk_clksrc)
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return rk_clksrc_init(np);
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pr_err("Too many timer definitions for '%s'\n", TIMER_NAME);
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return -EINVAL;
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}
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CLOCKSOURCE_OF_DECLARE(rk3288_timer, "rockchip,rk3288-timer", rk_timer_init);
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CLOCKSOURCE_OF_DECLARE(rk3399_timer, "rockchip,rk3399-timer", rk_timer_init);
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