drivers/perf: Add CCPI2 PMU support in ThunderX2 UNCORE driver.
CCPI2 is a low-latency high-bandwidth serial interface for inter socket connectivity of ThunderX2 processors. CCPI2 PMU supports up to 8 counters per socket. Counters are independently programmable to different events and can be started and stopped individually. The CCPI2 counters are 64-bit and do not overflow in normal operation. Signed-off-by: Ganapatrao Prabhakerrao Kulkarni <gkulkarni@marvell.com> Signed-off-by: Will Deacon <will@kernel.org>
This commit is contained in:
Ganapatrao Prabhakerrao Kulkarni
Will Deacon
parent
030f6f84e5
commit
5e2c27e833
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@ -16,23 +16,36 @@
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* they need to be sampled before overflow(i.e, at every 2 seconds).
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*/
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#define TX2_PMU_MAX_COUNTERS 4
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#define TX2_PMU_DMC_L3C_MAX_COUNTERS 4
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#define TX2_PMU_CCPI2_MAX_COUNTERS 8
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#define TX2_PMU_MAX_COUNTERS TX2_PMU_CCPI2_MAX_COUNTERS
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#define TX2_PMU_DMC_CHANNELS 8
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#define TX2_PMU_L3_TILES 16
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#define TX2_PMU_HRTIMER_INTERVAL (2 * NSEC_PER_SEC)
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#define GET_EVENTID(ev) ((ev->hw.config) & 0x1f)
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#define GET_COUNTERID(ev) ((ev->hw.idx) & 0x3)
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#define GET_EVENTID(ev, mask) ((ev->hw.config) & mask)
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#define GET_COUNTERID(ev, mask) ((ev->hw.idx) & mask)
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/* 1 byte per counter(4 counters).
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* Event id is encoded in bits [5:1] of a byte,
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*/
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#define DMC_EVENT_CFG(idx, val) ((val) << (((idx) * 8) + 1))
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/* bits[3:0] to select counters, are indexed from 8 to 15. */
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#define CCPI2_COUNTER_OFFSET 8
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#define L3C_COUNTER_CTL 0xA8
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#define L3C_COUNTER_DATA 0xAC
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#define DMC_COUNTER_CTL 0x234
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#define DMC_COUNTER_DATA 0x240
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#define CCPI2_PERF_CTL 0x108
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#define CCPI2_COUNTER_CTL 0x10C
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#define CCPI2_COUNTER_SEL 0x12c
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#define CCPI2_COUNTER_DATA_L 0x130
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#define CCPI2_COUNTER_DATA_H 0x134
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/* L3C event IDs */
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#define L3_EVENT_READ_REQ 0xD
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#define L3_EVENT_WRITEBACK_REQ 0xE
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@ -51,15 +64,28 @@
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#define DMC_EVENT_READ_TXNS 0xF
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#define DMC_EVENT_MAX 0x10
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#define CCPI2_EVENT_REQ_PKT_SENT 0x3D
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#define CCPI2_EVENT_SNOOP_PKT_SENT 0x65
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#define CCPI2_EVENT_DATA_PKT_SENT 0x105
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#define CCPI2_EVENT_GIC_PKT_SENT 0x12D
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#define CCPI2_EVENT_MAX 0x200
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#define CCPI2_PERF_CTL_ENABLE BIT(0)
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#define CCPI2_PERF_CTL_START BIT(1)
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#define CCPI2_PERF_CTL_RESET BIT(4)
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#define CCPI2_EVENT_LEVEL_RISING_EDGE BIT(10)
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#define CCPI2_EVENT_TYPE_EDGE_SENSITIVE BIT(11)
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enum tx2_uncore_type {
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PMU_TYPE_L3C,
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PMU_TYPE_DMC,
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PMU_TYPE_CCPI2,
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PMU_TYPE_INVALID,
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};
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/*
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* pmu on each socket has 2 uncore devices(dmc and l3c),
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* each device has 4 counters.
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* Each socket has 3 uncore devices associated with a PMU. The DMC and
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* L3C have 4 32-bit counters and the CCPI2 has 8 64-bit counters.
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*/
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struct tx2_uncore_pmu {
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struct hlist_node hpnode;
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@ -69,8 +95,10 @@ struct tx2_uncore_pmu {
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int node;
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int cpu;
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u32 max_counters;
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u32 counters_mask;
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u32 prorate_factor;
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u32 max_events;
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u32 events_mask;
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u64 hrtimer_interval;
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void __iomem *base;
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DECLARE_BITMAP(active_counters, TX2_PMU_MAX_COUNTERS);
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@ -79,6 +107,7 @@ struct tx2_uncore_pmu {
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struct hrtimer hrtimer;
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const struct attribute_group **attr_groups;
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enum tx2_uncore_type type;
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enum hrtimer_restart (*hrtimer_callback)(struct hrtimer *cb);
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void (*init_cntr_base)(struct perf_event *event,
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struct tx2_uncore_pmu *tx2_pmu);
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void (*stop_event)(struct perf_event *event);
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@ -92,7 +121,21 @@ static inline struct tx2_uncore_pmu *pmu_to_tx2_pmu(struct pmu *pmu)
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return container_of(pmu, struct tx2_uncore_pmu, pmu);
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}
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PMU_FORMAT_ATTR(event, "config:0-4");
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#define TX2_PMU_FORMAT_ATTR(_var, _name, _format) \
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static ssize_t \
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__tx2_pmu_##_var##_show(struct device *dev, \
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struct device_attribute *attr, \
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char *page) \
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{ \
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BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE); \
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return sprintf(page, _format "\n"); \
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} \
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\
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static struct device_attribute format_attr_##_var = \
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__ATTR(_name, 0444, __tx2_pmu_##_var##_show, NULL)
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TX2_PMU_FORMAT_ATTR(event, event, "config:0-4");
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TX2_PMU_FORMAT_ATTR(event_ccpi2, event, "config:0-9");
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static struct attribute *l3c_pmu_format_attrs[] = {
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&format_attr_event.attr,
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@ -104,6 +147,11 @@ static struct attribute *dmc_pmu_format_attrs[] = {
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NULL,
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};
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static struct attribute *ccpi2_pmu_format_attrs[] = {
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&format_attr_event_ccpi2.attr,
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NULL,
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};
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static const struct attribute_group l3c_pmu_format_attr_group = {
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.name = "format",
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.attrs = l3c_pmu_format_attrs,
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@ -114,6 +162,11 @@ static const struct attribute_group dmc_pmu_format_attr_group = {
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.attrs = dmc_pmu_format_attrs,
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};
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static const struct attribute_group ccpi2_pmu_format_attr_group = {
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.name = "format",
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.attrs = ccpi2_pmu_format_attrs,
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};
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/*
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* sysfs event attributes
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*/
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@ -164,6 +217,19 @@ static struct attribute *dmc_pmu_events_attrs[] = {
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NULL,
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};
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TX2_EVENT_ATTR(req_pktsent, CCPI2_EVENT_REQ_PKT_SENT);
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TX2_EVENT_ATTR(snoop_pktsent, CCPI2_EVENT_SNOOP_PKT_SENT);
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TX2_EVENT_ATTR(data_pktsent, CCPI2_EVENT_DATA_PKT_SENT);
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TX2_EVENT_ATTR(gic_pktsent, CCPI2_EVENT_GIC_PKT_SENT);
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static struct attribute *ccpi2_pmu_events_attrs[] = {
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&tx2_pmu_event_attr_req_pktsent.attr.attr,
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&tx2_pmu_event_attr_snoop_pktsent.attr.attr,
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&tx2_pmu_event_attr_data_pktsent.attr.attr,
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&tx2_pmu_event_attr_gic_pktsent.attr.attr,
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NULL,
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};
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static const struct attribute_group l3c_pmu_events_attr_group = {
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.name = "events",
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.attrs = l3c_pmu_events_attrs,
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@ -174,6 +240,11 @@ static const struct attribute_group dmc_pmu_events_attr_group = {
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.attrs = dmc_pmu_events_attrs,
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};
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static const struct attribute_group ccpi2_pmu_events_attr_group = {
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.name = "events",
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.attrs = ccpi2_pmu_events_attrs,
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};
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/*
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* sysfs cpumask attributes
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*/
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@ -213,6 +284,13 @@ static const struct attribute_group *dmc_pmu_attr_groups[] = {
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NULL
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};
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static const struct attribute_group *ccpi2_pmu_attr_groups[] = {
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&ccpi2_pmu_format_attr_group,
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&pmu_cpumask_attr_group,
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&ccpi2_pmu_events_attr_group,
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NULL
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};
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static inline u32 reg_readl(unsigned long addr)
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{
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return readl((void __iomem *)addr);
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@ -245,33 +323,58 @@ static void init_cntr_base_l3c(struct perf_event *event,
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struct tx2_uncore_pmu *tx2_pmu)
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{
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struct hw_perf_event *hwc = &event->hw;
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u32 cmask;
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tx2_pmu = pmu_to_tx2_pmu(event->pmu);
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cmask = tx2_pmu->counters_mask;
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/* counter ctrl/data reg offset at 8 */
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hwc->config_base = (unsigned long)tx2_pmu->base
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+ L3C_COUNTER_CTL + (8 * GET_COUNTERID(event));
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+ L3C_COUNTER_CTL + (8 * GET_COUNTERID(event, cmask));
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hwc->event_base = (unsigned long)tx2_pmu->base
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+ L3C_COUNTER_DATA + (8 * GET_COUNTERID(event));
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+ L3C_COUNTER_DATA + (8 * GET_COUNTERID(event, cmask));
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}
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static void init_cntr_base_dmc(struct perf_event *event,
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struct tx2_uncore_pmu *tx2_pmu)
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{
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struct hw_perf_event *hwc = &event->hw;
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u32 cmask;
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tx2_pmu = pmu_to_tx2_pmu(event->pmu);
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cmask = tx2_pmu->counters_mask;
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hwc->config_base = (unsigned long)tx2_pmu->base
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+ DMC_COUNTER_CTL;
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/* counter data reg offset at 0xc */
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hwc->event_base = (unsigned long)tx2_pmu->base
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+ DMC_COUNTER_DATA + (0xc * GET_COUNTERID(event));
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+ DMC_COUNTER_DATA + (0xc * GET_COUNTERID(event, cmask));
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}
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static void init_cntr_base_ccpi2(struct perf_event *event,
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struct tx2_uncore_pmu *tx2_pmu)
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{
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struct hw_perf_event *hwc = &event->hw;
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u32 cmask;
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cmask = tx2_pmu->counters_mask;
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hwc->config_base = (unsigned long)tx2_pmu->base
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+ CCPI2_COUNTER_CTL + (4 * GET_COUNTERID(event, cmask));
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hwc->event_base = (unsigned long)tx2_pmu->base;
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}
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static void uncore_start_event_l3c(struct perf_event *event, int flags)
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{
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u32 val;
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u32 val, emask;
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struct hw_perf_event *hwc = &event->hw;
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struct tx2_uncore_pmu *tx2_pmu;
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tx2_pmu = pmu_to_tx2_pmu(event->pmu);
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emask = tx2_pmu->events_mask;
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/* event id encoded in bits [07:03] */
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val = GET_EVENTID(event) << 3;
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val = GET_EVENTID(event, emask) << 3;
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reg_writel(val, hwc->config_base);
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local64_set(&hwc->prev_count, 0);
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reg_writel(0, hwc->event_base);
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@ -284,10 +387,17 @@ static inline void uncore_stop_event_l3c(struct perf_event *event)
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static void uncore_start_event_dmc(struct perf_event *event, int flags)
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{
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u32 val;
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u32 val, cmask, emask;
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struct hw_perf_event *hwc = &event->hw;
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int idx = GET_COUNTERID(event);
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int event_id = GET_EVENTID(event);
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struct tx2_uncore_pmu *tx2_pmu;
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int idx, event_id;
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tx2_pmu = pmu_to_tx2_pmu(event->pmu);
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cmask = tx2_pmu->counters_mask;
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emask = tx2_pmu->events_mask;
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idx = GET_COUNTERID(event, cmask);
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event_id = GET_EVENTID(event, emask);
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/* enable and start counters.
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* 8 bits for each counter, bits[05:01] of a counter to set event type.
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@ -302,9 +412,14 @@ static void uncore_start_event_dmc(struct perf_event *event, int flags)
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static void uncore_stop_event_dmc(struct perf_event *event)
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{
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u32 val;
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u32 val, cmask;
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struct hw_perf_event *hwc = &event->hw;
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int idx = GET_COUNTERID(event);
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struct tx2_uncore_pmu *tx2_pmu;
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int idx;
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tx2_pmu = pmu_to_tx2_pmu(event->pmu);
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cmask = tx2_pmu->counters_mask;
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idx = GET_COUNTERID(event, cmask);
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/* clear event type(bits[05:01]) to stop counter */
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val = reg_readl(hwc->config_base);
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@ -312,27 +427,72 @@ static void uncore_stop_event_dmc(struct perf_event *event)
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reg_writel(val, hwc->config_base);
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}
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static void uncore_start_event_ccpi2(struct perf_event *event, int flags)
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{
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u32 emask;
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struct hw_perf_event *hwc = &event->hw;
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struct tx2_uncore_pmu *tx2_pmu;
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tx2_pmu = pmu_to_tx2_pmu(event->pmu);
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emask = tx2_pmu->events_mask;
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/* Bit [09:00] to set event id.
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* Bits [10], set level to rising edge.
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* Bits [11], set type to edge sensitive.
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*/
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reg_writel((CCPI2_EVENT_TYPE_EDGE_SENSITIVE |
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CCPI2_EVENT_LEVEL_RISING_EDGE |
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GET_EVENTID(event, emask)), hwc->config_base);
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/* reset[4], enable[0] and start[1] counters */
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reg_writel(CCPI2_PERF_CTL_RESET |
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CCPI2_PERF_CTL_START |
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CCPI2_PERF_CTL_ENABLE,
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hwc->event_base + CCPI2_PERF_CTL);
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local64_set(&event->hw.prev_count, 0ULL);
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}
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static void uncore_stop_event_ccpi2(struct perf_event *event)
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{
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struct hw_perf_event *hwc = &event->hw;
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/* disable and stop counter */
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reg_writel(0, hwc->event_base + CCPI2_PERF_CTL);
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}
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static void tx2_uncore_event_update(struct perf_event *event)
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{
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s64 prev, delta, new = 0;
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u64 prev, delta, new = 0;
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struct hw_perf_event *hwc = &event->hw;
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struct tx2_uncore_pmu *tx2_pmu;
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enum tx2_uncore_type type;
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u32 prorate_factor;
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u32 cmask, emask;
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tx2_pmu = pmu_to_tx2_pmu(event->pmu);
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type = tx2_pmu->type;
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cmask = tx2_pmu->counters_mask;
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emask = tx2_pmu->events_mask;
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prorate_factor = tx2_pmu->prorate_factor;
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new = reg_readl(hwc->event_base);
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prev = local64_xchg(&hwc->prev_count, new);
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/* handles rollover of 32 bit counter */
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delta = (u32)(((1UL << 32) - prev) + new);
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if (type == PMU_TYPE_CCPI2) {
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reg_writel(CCPI2_COUNTER_OFFSET +
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GET_COUNTERID(event, cmask),
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hwc->event_base + CCPI2_COUNTER_SEL);
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new = reg_readl(hwc->event_base + CCPI2_COUNTER_DATA_H);
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new = (new << 32) +
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reg_readl(hwc->event_base + CCPI2_COUNTER_DATA_L);
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prev = local64_xchg(&hwc->prev_count, new);
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delta = new - prev;
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} else {
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new = reg_readl(hwc->event_base);
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prev = local64_xchg(&hwc->prev_count, new);
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/* handles rollover of 32 bit counter */
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delta = (u32)(((1UL << 32) - prev) + new);
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}
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/* DMC event data_transfers granularity is 16 Bytes, convert it to 64 */
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if (type == PMU_TYPE_DMC &&
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GET_EVENTID(event) == DMC_EVENT_DATA_TRANSFERS)
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GET_EVENTID(event, emask) == DMC_EVENT_DATA_TRANSFERS)
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delta = delta/4;
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/* L3C and DMC has 16 and 8 interleave channels respectively.
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@ -351,6 +511,7 @@ static enum tx2_uncore_type get_tx2_pmu_type(struct acpi_device *adev)
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} devices[] = {
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{"CAV901D", PMU_TYPE_L3C},
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{"CAV901F", PMU_TYPE_DMC},
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{"CAV901E", PMU_TYPE_CCPI2},
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{"", PMU_TYPE_INVALID}
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};
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@ -380,7 +541,8 @@ static bool tx2_uncore_validate_event(struct pmu *pmu,
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* Make sure the group of events can be scheduled at once
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* on the PMU.
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*/
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static bool tx2_uncore_validate_event_group(struct perf_event *event)
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static bool tx2_uncore_validate_event_group(struct perf_event *event,
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int max_counters)
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{
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struct perf_event *sibling, *leader = event->group_leader;
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int counters = 0;
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@ -403,7 +565,7 @@ static bool tx2_uncore_validate_event_group(struct perf_event *event)
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* If the group requires more counters than the HW has,
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* it cannot ever be scheduled.
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*/
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return counters <= TX2_PMU_MAX_COUNTERS;
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return counters <= max_counters;
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}
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@ -439,7 +601,7 @@ static int tx2_uncore_event_init(struct perf_event *event)
|
|||
hwc->config = event->attr.config;
|
||||
|
||||
/* Validate the group */
|
||||
if (!tx2_uncore_validate_event_group(event))
|
||||
if (!tx2_uncore_validate_event_group(event, tx2_pmu->max_counters))
|
||||
return -EINVAL;
|
||||
|
||||
return 0;
|
||||
|
|
@ -456,6 +618,10 @@ static void tx2_uncore_event_start(struct perf_event *event, int flags)
|
|||
tx2_pmu->start_event(event, flags);
|
||||
perf_event_update_userpage(event);
|
||||
|
||||
/* No hrtimer needed for CCPI2, 64-bit counters */
|
||||
if (!tx2_pmu->hrtimer_callback)
|
||||
return;
|
||||
|
||||
/* Start timer for first event */
|
||||
if (bitmap_weight(tx2_pmu->active_counters,
|
||||
tx2_pmu->max_counters) == 1) {
|
||||
|
|
@ -510,15 +676,23 @@ static void tx2_uncore_event_del(struct perf_event *event, int flags)
|
|||
{
|
||||
struct tx2_uncore_pmu *tx2_pmu = pmu_to_tx2_pmu(event->pmu);
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
u32 cmask;
|
||||
|
||||
cmask = tx2_pmu->counters_mask;
|
||||
tx2_uncore_event_stop(event, PERF_EF_UPDATE);
|
||||
|
||||
/* clear the assigned counter */
|
||||
free_counter(tx2_pmu, GET_COUNTERID(event));
|
||||
free_counter(tx2_pmu, GET_COUNTERID(event, cmask));
|
||||
|
||||
perf_event_update_userpage(event);
|
||||
tx2_pmu->events[hwc->idx] = NULL;
|
||||
hwc->idx = -1;
|
||||
|
||||
if (!tx2_pmu->hrtimer_callback)
|
||||
return;
|
||||
|
||||
if (bitmap_empty(tx2_pmu->active_counters, tx2_pmu->max_counters))
|
||||
hrtimer_cancel(&tx2_pmu->hrtimer);
|
||||
}
|
||||
|
||||
static void tx2_uncore_event_read(struct perf_event *event)
|
||||
|
|
@ -580,8 +754,12 @@ static int tx2_uncore_pmu_add_dev(struct tx2_uncore_pmu *tx2_pmu)
|
|||
cpu_online_mask);
|
||||
|
||||
tx2_pmu->cpu = cpu;
|
||||
hrtimer_init(&tx2_pmu->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
|
||||
tx2_pmu->hrtimer.function = tx2_hrtimer_callback;
|
||||
|
||||
if (tx2_pmu->hrtimer_callback) {
|
||||
hrtimer_init(&tx2_pmu->hrtimer,
|
||||
CLOCK_MONOTONIC, HRTIMER_MODE_REL);
|
||||
tx2_pmu->hrtimer.function = tx2_pmu->hrtimer_callback;
|
||||
}
|
||||
|
||||
ret = tx2_uncore_pmu_register(tx2_pmu);
|
||||
if (ret) {
|
||||
|
|
@ -653,10 +831,13 @@ static struct tx2_uncore_pmu *tx2_uncore_pmu_init_dev(struct device *dev,
|
|||
|
||||
switch (tx2_pmu->type) {
|
||||
case PMU_TYPE_L3C:
|
||||
tx2_pmu->max_counters = TX2_PMU_MAX_COUNTERS;
|
||||
tx2_pmu->max_counters = TX2_PMU_DMC_L3C_MAX_COUNTERS;
|
||||
tx2_pmu->counters_mask = 0x3;
|
||||
tx2_pmu->prorate_factor = TX2_PMU_L3_TILES;
|
||||
tx2_pmu->max_events = L3_EVENT_MAX;
|
||||
tx2_pmu->events_mask = 0x1f;
|
||||
tx2_pmu->hrtimer_interval = TX2_PMU_HRTIMER_INTERVAL;
|
||||
tx2_pmu->hrtimer_callback = tx2_hrtimer_callback;
|
||||
tx2_pmu->attr_groups = l3c_pmu_attr_groups;
|
||||
tx2_pmu->name = devm_kasprintf(dev, GFP_KERNEL,
|
||||
"uncore_l3c_%d", tx2_pmu->node);
|
||||
|
|
@ -665,10 +846,13 @@ static struct tx2_uncore_pmu *tx2_uncore_pmu_init_dev(struct device *dev,
|
|||
tx2_pmu->stop_event = uncore_stop_event_l3c;
|
||||
break;
|
||||
case PMU_TYPE_DMC:
|
||||
tx2_pmu->max_counters = TX2_PMU_MAX_COUNTERS;
|
||||
tx2_pmu->max_counters = TX2_PMU_DMC_L3C_MAX_COUNTERS;
|
||||
tx2_pmu->counters_mask = 0x3;
|
||||
tx2_pmu->prorate_factor = TX2_PMU_DMC_CHANNELS;
|
||||
tx2_pmu->max_events = DMC_EVENT_MAX;
|
||||
tx2_pmu->events_mask = 0x1f;
|
||||
tx2_pmu->hrtimer_interval = TX2_PMU_HRTIMER_INTERVAL;
|
||||
tx2_pmu->hrtimer_callback = tx2_hrtimer_callback;
|
||||
tx2_pmu->attr_groups = dmc_pmu_attr_groups;
|
||||
tx2_pmu->name = devm_kasprintf(dev, GFP_KERNEL,
|
||||
"uncore_dmc_%d", tx2_pmu->node);
|
||||
|
|
@ -676,6 +860,21 @@ static struct tx2_uncore_pmu *tx2_uncore_pmu_init_dev(struct device *dev,
|
|||
tx2_pmu->start_event = uncore_start_event_dmc;
|
||||
tx2_pmu->stop_event = uncore_stop_event_dmc;
|
||||
break;
|
||||
case PMU_TYPE_CCPI2:
|
||||
/* CCPI2 has 8 counters */
|
||||
tx2_pmu->max_counters = TX2_PMU_CCPI2_MAX_COUNTERS;
|
||||
tx2_pmu->counters_mask = 0x7;
|
||||
tx2_pmu->prorate_factor = 1;
|
||||
tx2_pmu->max_events = CCPI2_EVENT_MAX;
|
||||
tx2_pmu->events_mask = 0x1ff;
|
||||
tx2_pmu->attr_groups = ccpi2_pmu_attr_groups;
|
||||
tx2_pmu->name = devm_kasprintf(dev, GFP_KERNEL,
|
||||
"uncore_ccpi2_%d", tx2_pmu->node);
|
||||
tx2_pmu->init_cntr_base = init_cntr_base_ccpi2;
|
||||
tx2_pmu->start_event = uncore_start_event_ccpi2;
|
||||
tx2_pmu->stop_event = uncore_stop_event_ccpi2;
|
||||
tx2_pmu->hrtimer_callback = NULL;
|
||||
break;
|
||||
case PMU_TYPE_INVALID:
|
||||
devm_kfree(dev, tx2_pmu);
|
||||
return NULL;
|
||||
|
|
@ -744,7 +943,9 @@ static int tx2_uncore_pmu_offline_cpu(unsigned int cpu,
|
|||
if (cpu != tx2_pmu->cpu)
|
||||
return 0;
|
||||
|
||||
hrtimer_cancel(&tx2_pmu->hrtimer);
|
||||
if (tx2_pmu->hrtimer_callback)
|
||||
hrtimer_cancel(&tx2_pmu->hrtimer);
|
||||
|
||||
cpumask_copy(&cpu_online_mask_temp, cpu_online_mask);
|
||||
cpumask_clear_cpu(cpu, &cpu_online_mask_temp);
|
||||
new_cpu = cpumask_any_and(
|
||||
|
|
|
|||
Loading…
Reference in New Issue