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Merge commit 'refs/for-upstream/mali-dp' of git://linux-arm.org/linux-ld into drm-next 

This pull requests adds initial Mali D71 support into the Arm "komeda" DRM
driver. The code has been reviewed at the end of last year, I just been
too slow with pushing it into mainline. Since it started baking in
linux-next we had a kbuild-bot issue raised and one from Joe Perches on
the MAINTAINERS entry, for which I'm including fixes here.

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Liviu Dudau <Liviu.Dudau@arm.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190401192833.GW21747@e110455-lin.cambridge.arm.com
This commit is contained in:
Dave Airlie 2019-04-03 13:42:15 +10:00
parent 457109829f 04c8a1ec39
commit 5ebffda257
14 changed files with 1986 additions and 34 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
MAINTAINERS
View File

@ -1167,7 +1167,7 @@ S: Supported
T: git git://linux-arm.org/linux-ld.git for-upstream/mali-dp
F: drivers/gpu/drm/arm/display/include/
F: drivers/gpu/drm/arm/display/komeda/
F: Documentation/devicetree/bindings/display/arm/arm,komeda.txt
F: Documentation/devicetree/bindings/display/arm,komeda.txt
F: Documentation/gpu/komeda-kms.rst
ARM MALI-DP DRM DRIVER

31
drivers/gpu/drm/arm/display/include/malidp_utils.h
View File

@ -7,10 +7,41 @@
#ifndef _MALIDP_UTILS_
#define _MALIDP_UTILS_
#include <linux/delay.h>
#define has_bit(nr, mask) (BIT(nr) & (mask))
#define has_bits(bits, mask) (((bits) & (mask)) == (bits))
#define dp_for_each_set_bit(bit, mask) \
for_each_set_bit((bit), ((unsigned long *)&(mask)), sizeof(mask) * 8)
#define dp_wait_cond(__cond, __tries, __min_range, __max_range) \
({ \
int num_tries = __tries; \
while (!__cond && (num_tries > 0)) { \
usleep_range(__min_range, __max_range); \
if (__cond) \
break; \
num_tries--; \
} \
num_tries; \
})
/* the restriction of range is [start, end] */
struct malidp_range {
u32 start;
u32 end;
};
static inline void set_range(struct malidp_range *rg, u32 start, u32 end)
{
rg->start = start;
rg->end = end;
}
static inline bool in_range(struct malidp_range *rg, u32 v)
{
return (v >= rg->start) && (v <= rg->end);
}
#endif /* _MALIDP_UTILS_ */

3
drivers/gpu/drm/arm/display/komeda/Makefile
View File

@ -16,6 +16,7 @@ komeda-y := \
komeda_private_obj.o
komeda-y += \
d71/d71_dev.o
d71/d71_dev.o \
d71/d71_component.o
obj-$(CONFIG_DRM_KOMEDA) += komeda.o

684
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c Normal file
View File

@ -0,0 +1,684 @@
// SPDX-License-Identifier: GPL-2.0
/*
* (C) COPYRIGHT 2018 ARM Limited. All rights reserved.
* Author: James.Qian.Wang <james.qian.wang@arm.com>
*
*/
#include <drm/drm_print.h>
#include "d71_dev.h"
#include "komeda_kms.h"
#include "malidp_io.h"
#include "komeda_framebuffer.h"
static void get_resources_id(u32 hw_id, u32 *pipe_id, u32 *comp_id)
{
u32 id = BLOCK_INFO_BLK_ID(hw_id);
u32 pipe = id;
switch (BLOCK_INFO_BLK_TYPE(hw_id)) {
case D71_BLK_TYPE_LPU_WB_LAYER:
id = KOMEDA_COMPONENT_WB_LAYER;
break;
case D71_BLK_TYPE_CU_SPLITTER:
id = KOMEDA_COMPONENT_SPLITTER;
break;
case D71_BLK_TYPE_CU_SCALER:
pipe = id / D71_PIPELINE_MAX_SCALERS;
id %= D71_PIPELINE_MAX_SCALERS;
id += KOMEDA_COMPONENT_SCALER0;
break;
case D71_BLK_TYPE_CU:
id += KOMEDA_COMPONENT_COMPIZ0;
break;
case D71_BLK_TYPE_LPU_LAYER:
pipe = id / D71_PIPELINE_MAX_LAYERS;
id %= D71_PIPELINE_MAX_LAYERS;
id += KOMEDA_COMPONENT_LAYER0;
break;
case D71_BLK_TYPE_DOU_IPS:
id += KOMEDA_COMPONENT_IPS0;
break;
case D71_BLK_TYPE_CU_MERGER:
id = KOMEDA_COMPONENT_MERGER;
break;
case D71_BLK_TYPE_DOU:
id = KOMEDA_COMPONENT_TIMING_CTRLR;
break;
default:
id = 0xFFFFFFFF;
}
if (comp_id)
*comp_id = id;
if (pipe_id)
*pipe_id = pipe;
}
static u32 get_valid_inputs(struct block_header *blk)
{
u32 valid_inputs = 0, comp_id;
int i;
for (i = 0; i < PIPELINE_INFO_N_VALID_INPUTS(blk->pipeline_info); i++) {
get_resources_id(blk->input_ids[i], NULL, &comp_id);
if (comp_id == 0xFFFFFFFF)
continue;
valid_inputs |= BIT(comp_id);
}
return valid_inputs;
}
static void get_values_from_reg(void __iomem *reg, u32 offset,
u32 count, u32 *val)
{
u32 i, addr;
for (i = 0; i < count; i++) {
addr = offset + (i << 2);
/* 0xA4 is WO register */
if (addr != 0xA4)
val[i] = malidp_read32(reg, addr);
else
val[i] = 0xDEADDEAD;
}
}
static void dump_block_header(struct seq_file *sf, void __iomem *reg)
{
struct block_header hdr;
u32 i, n_input, n_output;
d71_read_block_header(reg, &hdr);
seq_printf(sf, "BLOCK_INFO:\t\t0x%X\n", hdr.block_info);
seq_printf(sf, "PIPELINE_INFO:\t\t0x%X\n", hdr.pipeline_info);
n_output = PIPELINE_INFO_N_OUTPUTS(hdr.pipeline_info);
n_input = PIPELINE_INFO_N_VALID_INPUTS(hdr.pipeline_info);
for (i = 0; i < n_input; i++)
seq_printf(sf, "VALID_INPUT_ID%u:\t0x%X\n",
i, hdr.input_ids[i]);
for (i = 0; i < n_output; i++)
seq_printf(sf, "OUTPUT_ID%u:\t\t0x%X\n",
i, hdr.output_ids[i]);
}
static u32 to_rot_ctrl(u32 rot)
{
u32 lr_ctrl = 0;
switch (rot & DRM_MODE_ROTATE_MASK) {
case DRM_MODE_ROTATE_0:
lr_ctrl |= L_ROT(L_ROT_R0);
break;
case DRM_MODE_ROTATE_90:
lr_ctrl |= L_ROT(L_ROT_R90);
break;
case DRM_MODE_ROTATE_180:
lr_ctrl |= L_ROT(L_ROT_R180);
break;
case DRM_MODE_ROTATE_270:
lr_ctrl |= L_ROT(L_ROT_R270);
break;
}
if (rot & DRM_MODE_REFLECT_X)
lr_ctrl |= L_HFLIP;
if (rot & DRM_MODE_REFLECT_Y)
lr_ctrl |= L_VFLIP;
return lr_ctrl;
}
static inline u32 to_d71_input_id(struct komeda_component_output *output)
{
struct komeda_component *comp = output->component;
return comp ? (comp->hw_id + output->output_port) : 0;
}
static void d71_layer_disable(struct komeda_component *c)
{
malidp_write32_mask(c->reg, BLK_CONTROL, L_EN, 0);
}
static void d71_layer_update(struct komeda_component *c,
struct komeda_component_state *state)
{
struct komeda_layer_state *st = to_layer_st(state);
struct drm_plane_state *plane_st = state->plane->state;
struct drm_framebuffer *fb = plane_st->fb;
struct komeda_fb *kfb = to_kfb(fb);
u32 __iomem *reg = c->reg;
u32 ctrl_mask = L_EN | L_ROT(L_ROT_R270) | L_HFLIP | L_VFLIP | L_TBU_EN;
u32 ctrl = L_EN | to_rot_ctrl(st->rot);
int i;
for (i = 0; i < fb->format->num_planes; i++) {
malidp_write32(reg,
BLK_P0_PTR_LOW + i * LAYER_PER_PLANE_REGS * 4,
lower_32_bits(st->addr[i]));
malidp_write32(reg,
BLK_P0_PTR_HIGH + i * LAYER_PER_PLANE_REGS * 4,
upper_32_bits(st->addr[i]));
if (i >= 2)
break;
malidp_write32(reg,
BLK_P0_STRIDE + i * LAYER_PER_PLANE_REGS * 4,
fb->pitches[i] & 0xFFFF);
}
malidp_write32(reg, LAYER_FMT, kfb->format_caps->hw_id);
malidp_write32(reg, BLK_IN_SIZE, HV_SIZE(st->hsize, st->vsize));
malidp_write32_mask(reg, BLK_CONTROL, ctrl_mask, ctrl);
}
static void d71_layer_dump(struct komeda_component *c, struct seq_file *sf)
{
u32 v[15], i;
bool rich, rgb2rgb;
char *prefix;
get_values_from_reg(c->reg, LAYER_INFO, 1, &v[14]);
if (v[14] & 0x1) {
rich = true;
prefix = "LR_";
} else {
rich = false;
prefix = "LS_";
}
rgb2rgb = !!(v[14] & L_INFO_CM);
dump_block_header(sf, c->reg);
seq_printf(sf, "%sLAYER_INFO:\t\t0x%X\n", prefix, v[14]);
get_values_from_reg(c->reg, 0xD0, 1, v);
seq_printf(sf, "%sCONTROL:\t\t0x%X\n", prefix, v[0]);
if (rich) {
get_values_from_reg(c->reg, 0xD4, 1, v);
seq_printf(sf, "LR_RICH_CONTROL:\t0x%X\n", v[0]);
}
get_values_from_reg(c->reg, 0xD8, 4, v);
seq_printf(sf, "%sFORMAT:\t\t0x%X\n", prefix, v[0]);
seq_printf(sf, "%sIT_COEFFTAB:\t\t0x%X\n", prefix, v[1]);
seq_printf(sf, "%sIN_SIZE:\t\t0x%X\n", prefix, v[2]);
seq_printf(sf, "%sPALPHA:\t\t0x%X\n", prefix, v[3]);
get_values_from_reg(c->reg, 0x100, 3, v);
seq_printf(sf, "%sP0_PTR_LOW:\t\t0x%X\n", prefix, v[0]);
seq_printf(sf, "%sP0_PTR_HIGH:\t\t0x%X\n", prefix, v[1]);
seq_printf(sf, "%sP0_STRIDE:\t\t0x%X\n", prefix, v[2]);
get_values_from_reg(c->reg, 0x110, 2, v);
seq_printf(sf, "%sP1_PTR_LOW:\t\t0x%X\n", prefix, v[0]);
seq_printf(sf, "%sP1_PTR_HIGH:\t\t0x%X\n", prefix, v[1]);
if (rich) {
get_values_from_reg(c->reg, 0x118, 1, v);
seq_printf(sf, "LR_P1_STRIDE:\t\t0x%X\n", v[0]);
get_values_from_reg(c->reg, 0x120, 2, v);
seq_printf(sf, "LR_P2_PTR_LOW:\t\t0x%X\n", v[0]);
seq_printf(sf, "LR_P2_PTR_HIGH:\t\t0x%X\n", v[1]);
get_values_from_reg(c->reg, 0x130, 12, v);
for (i = 0; i < 12; i++)
seq_printf(sf, "LR_YUV_RGB_COEFF%u:\t0x%X\n", i, v[i]);
}
if (rgb2rgb) {
get_values_from_reg(c->reg, LAYER_RGB_RGB_COEFF0, 12, v);
for (i = 0; i < 12; i++)
seq_printf(sf, "LS_RGB_RGB_COEFF%u:\t0x%X\n", i, v[i]);
}
get_values_from_reg(c->reg, 0x160, 3, v);
seq_printf(sf, "%sAD_CONTROL:\t\t0x%X\n", prefix, v[0]);
seq_printf(sf, "%sAD_H_CROP:\t\t0x%X\n", prefix, v[1]);
seq_printf(sf, "%sAD_V_CROP:\t\t0x%X\n", prefix, v[2]);
}
static struct komeda_component_funcs d71_layer_funcs = {
.update = d71_layer_update,
.disable = d71_layer_disable,
.dump_register = d71_layer_dump,
};
static int d71_layer_init(struct d71_dev *d71,
struct block_header *blk, u32 __iomem *reg)
{
struct komeda_component *c;
struct komeda_layer *layer;
u32 pipe_id, layer_id, layer_info;
get_resources_id(blk->block_info, &pipe_id, &layer_id);
c = komeda_component_add(&d71->pipes[pipe_id]->base, sizeof(*layer),
layer_id,
BLOCK_INFO_INPUT_ID(blk->block_info),
&d71_layer_funcs, 0,
get_valid_inputs(blk),
1, reg, "LPU%d_LAYER%d", pipe_id, layer_id);
if (IS_ERR(c)) {
DRM_ERROR("Failed to add layer component\n");
return PTR_ERR(c);
}
layer = to_layer(c);
layer_info = malidp_read32(reg, LAYER_INFO);
if (layer_info & L_INFO_RF)
layer->layer_type = KOMEDA_FMT_RICH_LAYER;
else
layer->layer_type = KOMEDA_FMT_SIMPLE_LAYER;
set_range(&layer->hsize_in, 4, d71->max_line_size);
set_range(&layer->vsize_in, 4, d71->max_vsize);
malidp_write32(reg, LAYER_PALPHA, D71_PALPHA_DEF_MAP);
layer->supported_rots = DRM_MODE_ROTATE_MASK | DRM_MODE_REFLECT_MASK;
return 0;
}
static int d71_wb_layer_init(struct d71_dev *d71,
struct block_header *blk, u32 __iomem *reg)
{
DRM_DEBUG("Detect D71_Wb_Layer.\n");
return 0;
}
static void d71_component_disable(struct komeda_component *c)
{
u32 __iomem *reg = c->reg;
u32 i;
malidp_write32(reg, BLK_CONTROL, 0);
for (i = 0; i < c->max_active_inputs; i++)
malidp_write32(reg, BLK_INPUT_ID0 + (i << 2), 0);
}
static void compiz_enable_input(u32 __iomem *id_reg,
u32 __iomem *cfg_reg,
u32 input_hw_id,
struct komeda_compiz_input_cfg *cin)
{
u32 ctrl = CU_INPUT_CTRL_EN;
u8 blend = cin->pixel_blend_mode;
if (blend == DRM_MODE_BLEND_PIXEL_NONE)
ctrl |= CU_INPUT_CTRL_PAD;
else if (blend == DRM_MODE_BLEND_PREMULTI)
ctrl |= CU_INPUT_CTRL_PMUL;
ctrl |= CU_INPUT_CTRL_ALPHA(cin->layer_alpha);
malidp_write32(id_reg, BLK_INPUT_ID0, input_hw_id);
malidp_write32(cfg_reg, CU_INPUT0_SIZE,
HV_SIZE(cin->hsize, cin->vsize));
malidp_write32(cfg_reg, CU_INPUT0_OFFSET,
HV_OFFSET(cin->hoffset, cin->voffset));
malidp_write32(cfg_reg, CU_INPUT0_CONTROL, ctrl);
}
static void d71_compiz_update(struct komeda_component *c,
struct komeda_component_state *state)
{
struct komeda_compiz_state *st = to_compiz_st(state);
u32 __iomem *reg = c->reg;
u32 __iomem *id_reg, *cfg_reg;
u32 index, input_hw_id;
for_each_changed_input(state, index) {
id_reg = reg + index;
cfg_reg = reg + index * CU_PER_INPUT_REGS;
input_hw_id = to_d71_input_id(&state->inputs[index]);
if (state->active_inputs & BIT(index)) {
compiz_enable_input(id_reg, cfg_reg,
input_hw_id, &st->cins[index]);
} else {
malidp_write32(id_reg, BLK_INPUT_ID0, 0);
malidp_write32(cfg_reg, CU_INPUT0_CONTROL, 0);
}
}
malidp_write32(reg, BLK_SIZE, HV_SIZE(st->hsize, st->vsize));
}
static void d71_compiz_dump(struct komeda_component *c, struct seq_file *sf)
{
u32 v[8], i;
dump_block_header(sf, c->reg);
get_values_from_reg(c->reg, 0x80, 5, v);
for (i = 0; i < 5; i++)
seq_printf(sf, "CU_INPUT_ID%u:\t\t0x%X\n", i, v[i]);
get_values_from_reg(c->reg, 0xA0, 5, v);
seq_printf(sf, "CU_IRQ_RAW_STATUS:\t0x%X\n", v[0]);
seq_printf(sf, "CU_IRQ_CLEAR:\t\t0x%X\n", v[1]);
seq_printf(sf, "CU_IRQ_MASK:\t\t0x%X\n", v[2]);
seq_printf(sf, "CU_IRQ_STATUS:\t\t0x%X\n", v[3]);
seq_printf(sf, "CU_STATUS:\t\t0x%X\n", v[4]);
get_values_from_reg(c->reg, 0xD0, 2, v);
seq_printf(sf, "CU_CONTROL:\t\t0x%X\n", v[0]);
seq_printf(sf, "CU_SIZE:\t\t0x%X\n", v[1]);
get_values_from_reg(c->reg, 0xDC, 1, v);
seq_printf(sf, "CU_BG_COLOR:\t\t0x%X\n", v[0]);
for (i = 0, v[4] = 0xE0; i < 5; i++, v[4] += 0x10) {
get_values_from_reg(c->reg, v[4], 3, v);
seq_printf(sf, "CU_INPUT%u_SIZE:\t\t0x%X\n", i, v[0]);
seq_printf(sf, "CU_INPUT%u_OFFSET:\t0x%X\n", i, v[1]);
seq_printf(sf, "CU_INPUT%u_CONTROL:\t0x%X\n", i, v[2]);
}
get_values_from_reg(c->reg, 0x130, 2, v);
seq_printf(sf, "CU_USER_LOW:\t\t0x%X\n", v[0]);
seq_printf(sf, "CU_USER_HIGH:\t\t0x%X\n", v[1]);
}
struct komeda_component_funcs d71_compiz_funcs = {
.update = d71_compiz_update,
.disable = d71_component_disable,
.dump_register = d71_compiz_dump,
};
static int d71_compiz_init(struct d71_dev *d71,
struct block_header *blk, u32 __iomem *reg)
{
struct komeda_component *c;
struct komeda_compiz *compiz;
u32 pipe_id, comp_id;
get_resources_id(blk->block_info, &pipe_id, &comp_id);
c = komeda_component_add(&d71->pipes[pipe_id]->base, sizeof(*compiz),
comp_id,
BLOCK_INFO_INPUT_ID(blk->block_info),
&d71_compiz_funcs,
CU_NUM_INPUT_IDS, get_valid_inputs(blk),
CU_NUM_OUTPUT_IDS, reg,
"CU%d", pipe_id);
if (IS_ERR(c))
return PTR_ERR(c);
compiz = to_compiz(c);
set_range(&compiz->hsize, D71_MIN_LINE_SIZE, d71->max_line_size);
set_range(&compiz->vsize, D71_MIN_VERTICAL_SIZE, d71->max_vsize);
return 0;
}
static void d71_improc_update(struct komeda_component *c,
struct komeda_component_state *state)
{
struct komeda_improc_state *st = to_improc_st(state);
u32 __iomem *reg = c->reg;
u32 index, input_hw_id;
for_each_changed_input(state, index) {
input_hw_id = state->active_inputs & BIT(index) ?
to_d71_input_id(&state->inputs[index]) : 0;
malidp_write32(reg, BLK_INPUT_ID0 + index * 4, input_hw_id);
}
malidp_write32(reg, BLK_SIZE, HV_SIZE(st->hsize, st->vsize));
}
static void d71_improc_dump(struct komeda_component *c, struct seq_file *sf)
{
u32 v[12], i;
dump_block_header(sf, c->reg);
get_values_from_reg(c->reg, 0x80, 2, v);
seq_printf(sf, "IPS_INPUT_ID0:\t\t0x%X\n", v[0]);
seq_printf(sf, "IPS_INPUT_ID1:\t\t0x%X\n", v[1]);
get_values_from_reg(c->reg, 0xC0, 1, v);
seq_printf(sf, "IPS_INFO:\t\t0x%X\n", v[0]);
get_values_from_reg(c->reg, 0xD0, 3, v);
seq_printf(sf, "IPS_CONTROL:\t\t0x%X\n", v[0]);
seq_printf(sf, "IPS_SIZE:\t\t0x%X\n", v[1]);
seq_printf(sf, "IPS_DEPTH:\t\t0x%X\n", v[2]);
get_values_from_reg(c->reg, 0x130, 12, v);
for (i = 0; i < 12; i++)
seq_printf(sf, "IPS_RGB_RGB_COEFF%u:\t0x%X\n", i, v[i]);
get_values_from_reg(c->reg, 0x170, 12, v);
for (i = 0; i < 12; i++)
seq_printf(sf, "IPS_RGB_YUV_COEFF%u:\t0x%X\n", i, v[i]);
}
struct komeda_component_funcs d71_improc_funcs = {
.update = d71_improc_update,
.disable = d71_component_disable,
.dump_register = d71_improc_dump,
};
static int d71_improc_init(struct d71_dev *d71,
struct block_header *blk, u32 __iomem *reg)
{
struct komeda_component *c;
struct komeda_improc *improc;
u32 pipe_id, comp_id, value;
get_resources_id(blk->block_info, &pipe_id, &comp_id);
c = komeda_component_add(&d71->pipes[pipe_id]->base, sizeof(*improc),
comp_id,
BLOCK_INFO_INPUT_ID(blk->block_info),
&d71_improc_funcs, IPS_NUM_INPUT_IDS,
get_valid_inputs(blk),
IPS_NUM_OUTPUT_IDS, reg, "DOU%d_IPS", pipe_id);
if (IS_ERR(c)) {
DRM_ERROR("Failed to add improc component\n");
return PTR_ERR(c);
}
improc = to_improc(c);
improc->supported_color_depths = BIT(8) | BIT(10);
improc->supported_color_formats = DRM_COLOR_FORMAT_RGB444 |
DRM_COLOR_FORMAT_YCRCB444 |
DRM_COLOR_FORMAT_YCRCB422;
value = malidp_read32(reg, BLK_INFO);
if (value & IPS_INFO_CHD420)
improc->supported_color_formats |= DRM_COLOR_FORMAT_YCRCB420;
improc->supports_csc = true;
improc->supports_gamma = true;
return 0;
}
static void d71_timing_ctrlr_disable(struct komeda_component *c)
{
malidp_write32_mask(c->reg, BLK_CONTROL, BS_CTRL_EN, 0);
}
static void d71_timing_ctrlr_update(struct komeda_component *c,
struct komeda_component_state *state)
{
struct drm_crtc_state *crtc_st = state->crtc->state;
u32 __iomem *reg = c->reg;
struct videomode vm;
u32 value;
drm_display_mode_to_videomode(&crtc_st->adjusted_mode, &vm);
malidp_write32(reg, BS_ACTIVESIZE, HV_SIZE(vm.hactive, vm.vactive));
malidp_write32(reg, BS_HINTERVALS, BS_H_INTVALS(vm.hfront_porch,
vm.hback_porch));
malidp_write32(reg, BS_VINTERVALS, BS_V_INTVALS(vm.vfront_porch,
vm.vback_porch));
value = BS_SYNC_VSW(vm.vsync_len) | BS_SYNC_HSW(vm.hsync_len);
value |= vm.flags & DISPLAY_FLAGS_VSYNC_HIGH ? BS_SYNC_VSP : 0;
value |= vm.flags & DISPLAY_FLAGS_HSYNC_HIGH ? BS_SYNC_HSP : 0;
malidp_write32(reg, BS_SYNC, value);
malidp_write32(reg, BS_PROG_LINE, D71_DEFAULT_PREPRETCH_LINE - 1);
malidp_write32(reg, BS_PREFETCH_LINE, D71_DEFAULT_PREPRETCH_LINE);
/* configure bs control register */
value = BS_CTRL_EN | BS_CTRL_VM;
malidp_write32(reg, BLK_CONTROL, value);
}
void d71_timing_ctrlr_dump(struct komeda_component *c, struct seq_file *sf)
{
u32 v[8], i;
dump_block_header(sf, c->reg);
get_values_from_reg(c->reg, 0xC0, 1, v);
seq_printf(sf, "BS_INFO:\t\t0x%X\n", v[0]);
get_values_from_reg(c->reg, 0xD0, 8, v);
seq_printf(sf, "BS_CONTROL:\t\t0x%X\n", v[0]);
seq_printf(sf, "BS_PROG_LINE:\t\t0x%X\n", v[1]);
seq_printf(sf, "BS_PREFETCH_LINE:\t0x%X\n", v[2]);
seq_printf(sf, "BS_BG_COLOR:\t\t0x%X\n", v[3]);
seq_printf(sf, "BS_ACTIVESIZE:\t\t0x%X\n", v[4]);
seq_printf(sf, "BS_HINTERVALS:\t\t0x%X\n", v[5]);
seq_printf(sf, "BS_VINTERVALS:\t\t0x%X\n", v[6]);
seq_printf(sf, "BS_SYNC:\t\t0x%X\n", v[7]);
get_values_from_reg(c->reg, 0x100, 3, v);
seq_printf(sf, "BS_DRIFT_TO:\t\t0x%X\n", v[0]);
seq_printf(sf, "BS_FRAME_TO:\t\t0x%X\n", v[1]);
seq_printf(sf, "BS_TE_TO:\t\t0x%X\n", v[2]);
get_values_from_reg(c->reg, 0x110, 3, v);
for (i = 0; i < 3; i++)
seq_printf(sf, "BS_T%u_INTERVAL:\t\t0x%X\n", i, v[i]);
get_values_from_reg(c->reg, 0x120, 5, v);
for (i = 0; i < 2; i++) {
seq_printf(sf, "BS_CRC%u_LOW:\t\t0x%X\n", i, v[i << 1]);
seq_printf(sf, "BS_CRC%u_HIGH:\t\t0x%X\n", i, v[(i << 1) + 1]);
}
seq_printf(sf, "BS_USER:\t\t0x%X\n", v[4]);
}
struct komeda_component_funcs d71_timing_ctrlr_funcs = {
.update = d71_timing_ctrlr_update,
.disable = d71_timing_ctrlr_disable,
.dump_register = d71_timing_ctrlr_dump,
};
static int d71_timing_ctrlr_init(struct d71_dev *d71,
struct block_header *blk, u32 __iomem *reg)
{
struct komeda_component *c;
struct komeda_timing_ctrlr *ctrlr;
u32 pipe_id, comp_id;
get_resources_id(blk->block_info, &pipe_id, &comp_id);
c = komeda_component_add(&d71->pipes[pipe_id]->base, sizeof(*ctrlr),
KOMEDA_COMPONENT_TIMING_CTRLR,
BLOCK_INFO_INPUT_ID(blk->block_info),
&d71_timing_ctrlr_funcs,
1, BIT(KOMEDA_COMPONENT_IPS0 + pipe_id),
BS_NUM_OUTPUT_IDS, reg, "DOU%d_BS", pipe_id);
if (IS_ERR(c)) {
DRM_ERROR("Failed to add display_ctrl component\n");
return PTR_ERR(c);
}
ctrlr = to_ctrlr(c);
ctrlr->supports_dual_link = true;
return 0;
}
int d71_probe_block(struct d71_dev *d71,
struct block_header *blk, u32 __iomem *reg)
{
struct d71_pipeline *pipe;
int blk_id = BLOCK_INFO_BLK_ID(blk->block_info);
int err = 0;
switch (BLOCK_INFO_BLK_TYPE(blk->block_info)) {
case D71_BLK_TYPE_GCU:
break;
case D71_BLK_TYPE_LPU:
pipe = d71->pipes[blk_id];
pipe->lpu_addr = reg;
break;
case D71_BLK_TYPE_LPU_LAYER:
err = d71_layer_init(d71, blk, reg);
break;
case D71_BLK_TYPE_LPU_WB_LAYER:
err = d71_wb_layer_init(d71, blk, reg);
break;
case D71_BLK_TYPE_CU:
pipe = d71->pipes[blk_id];
pipe->cu_addr = reg;
err = d71_compiz_init(d71, blk, reg);
break;
case D71_BLK_TYPE_CU_SPLITTER:
case D71_BLK_TYPE_CU_SCALER:
case D71_BLK_TYPE_CU_MERGER:
break;
case D71_BLK_TYPE_DOU:
pipe = d71->pipes[blk_id];
pipe->dou_addr = reg;
break;
case D71_BLK_TYPE_DOU_IPS:
err = d71_improc_init(d71, blk, reg);
break;
case D71_BLK_TYPE_DOU_FT_COEFF:
pipe = d71->pipes[blk_id];
pipe->dou_ft_coeff_addr = reg;
break;
case D71_BLK_TYPE_DOU_BS:
err = d71_timing_ctrlr_init(d71, blk, reg);
break;
case D71_BLK_TYPE_GLB_LT_COEFF:
break;
case D71_BLK_TYPE_GLB_SCL_COEFF:
d71->glb_scl_coeff_addr[blk_id] = reg;
break;
default:
DRM_ERROR("Unknown block (block_info: 0x%x) is found\n",
blk->block_info);
err = -EINVAL;
break;
}
return err;
}

377
drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
View File

@ -4,13 +4,375 @@
* Author: James.Qian.Wang <james.qian.wang@arm.com>
*
*/
#include <drm/drm_print.h>
#include "d71_dev.h"
#include "malidp_io.h"
#include "komeda_dev.h"
static u64 get_lpu_event(struct d71_pipeline *d71_pipeline)
{
u32 __iomem *reg = d71_pipeline->lpu_addr;
u32 status, raw_status;
u64 evts = 0ULL;
raw_status = malidp_read32(reg, BLK_IRQ_RAW_STATUS);
if (raw_status & LPU_IRQ_IBSY)
evts |= KOMEDA_EVENT_IBSY;
if (raw_status & LPU_IRQ_EOW)
evts |= KOMEDA_EVENT_EOW;
if (raw_status & (LPU_IRQ_ERR | LPU_IRQ_IBSY)) {
u32 restore = 0, tbu_status;
/* Check error of LPU status */
status = malidp_read32(reg, BLK_STATUS);
if (status & LPU_STATUS_AXIE) {
restore |= LPU_STATUS_AXIE;
evts |= KOMEDA_ERR_AXIE;
}
if (status & LPU_STATUS_ACE0) {
restore |= LPU_STATUS_ACE0;
evts |= KOMEDA_ERR_ACE0;
}
if (status & LPU_STATUS_ACE1) {
restore |= LPU_STATUS_ACE1;
evts |= KOMEDA_ERR_ACE1;
}
if (status & LPU_STATUS_ACE2) {
restore |= LPU_STATUS_ACE2;
evts |= KOMEDA_ERR_ACE2;
}
if (status & LPU_STATUS_ACE3) {
restore |= LPU_STATUS_ACE3;
evts |= KOMEDA_ERR_ACE3;
}
if (restore != 0)
malidp_write32_mask(reg, BLK_STATUS, restore, 0);
restore = 0;
/* Check errors of TBU status */
tbu_status = malidp_read32(reg, LPU_TBU_STATUS);
if (tbu_status & LPU_TBU_STATUS_TCF) {
restore |= LPU_TBU_STATUS_TCF;
evts |= KOMEDA_ERR_TCF;
}
if (tbu_status & LPU_TBU_STATUS_TTNG) {
restore |= LPU_TBU_STATUS_TTNG;
evts |= KOMEDA_ERR_TTNG;
}
if (tbu_status & LPU_TBU_STATUS_TITR) {
restore |= LPU_TBU_STATUS_TITR;
evts |= KOMEDA_ERR_TITR;
}
if (tbu_status & LPU_TBU_STATUS_TEMR) {
restore |= LPU_TBU_STATUS_TEMR;
evts |= KOMEDA_ERR_TEMR;
}
if (tbu_status & LPU_TBU_STATUS_TTF) {
restore |= LPU_TBU_STATUS_TTF;
evts |= KOMEDA_ERR_TTF;
}
if (restore != 0)
malidp_write32_mask(reg, LPU_TBU_STATUS, restore, 0);
}
malidp_write32(reg, BLK_IRQ_CLEAR, raw_status);
return evts;
}
static u64 get_cu_event(struct d71_pipeline *d71_pipeline)
{
u32 __iomem *reg = d71_pipeline->cu_addr;
u32 status, raw_status;
u64 evts = 0ULL;
raw_status = malidp_read32(reg, BLK_IRQ_RAW_STATUS);
if (raw_status & CU_IRQ_OVR)
evts |= KOMEDA_EVENT_OVR;
if (raw_status & (CU_IRQ_ERR | CU_IRQ_OVR)) {
status = malidp_read32(reg, BLK_STATUS) & 0x7FFFFFFF;
if (status & CU_STATUS_CPE)
evts |= KOMEDA_ERR_CPE;
if (status & CU_STATUS_ZME)
evts |= KOMEDA_ERR_ZME;
if (status & CU_STATUS_CFGE)
evts |= KOMEDA_ERR_CFGE;
if (status)
malidp_write32_mask(reg, BLK_STATUS, status, 0);
}
malidp_write32(reg, BLK_IRQ_CLEAR, raw_status);
return evts;
}
static u64 get_dou_event(struct d71_pipeline *d71_pipeline)
{
u32 __iomem *reg = d71_pipeline->dou_addr;
u32 status, raw_status;
u64 evts = 0ULL;
raw_status = malidp_read32(reg, BLK_IRQ_RAW_STATUS);
if (raw_status & DOU_IRQ_PL0)
evts |= KOMEDA_EVENT_VSYNC;
if (raw_status & DOU_IRQ_UND)
evts |= KOMEDA_EVENT_URUN;
if (raw_status & (DOU_IRQ_ERR | DOU_IRQ_UND)) {
u32 restore = 0;
status = malidp_read32(reg, BLK_STATUS);
if (status & DOU_STATUS_DRIFTTO) {
restore |= DOU_STATUS_DRIFTTO;
evts |= KOMEDA_ERR_DRIFTTO;
}
if (status & DOU_STATUS_FRAMETO) {
restore |= DOU_STATUS_FRAMETO;
evts |= KOMEDA_ERR_FRAMETO;
}
if (status & DOU_STATUS_TETO) {
restore |= DOU_STATUS_TETO;
evts |= KOMEDA_ERR_TETO;
}
if (status & DOU_STATUS_CSCE) {
restore |= DOU_STATUS_CSCE;
evts |= KOMEDA_ERR_CSCE;
}
if (restore != 0)
malidp_write32_mask(reg, BLK_STATUS, restore, 0);
}
malidp_write32(reg, BLK_IRQ_CLEAR, raw_status);
return evts;
}
static u64 get_pipeline_event(struct d71_pipeline *d71_pipeline, u32 gcu_status)
{
u32 evts = 0ULL;
if (gcu_status & (GLB_IRQ_STATUS_LPU0 | GLB_IRQ_STATUS_LPU1))
evts |= get_lpu_event(d71_pipeline);
if (gcu_status & (GLB_IRQ_STATUS_CU0 | GLB_IRQ_STATUS_CU1))
evts |= get_cu_event(d71_pipeline);
if (gcu_status & (GLB_IRQ_STATUS_DOU0 | GLB_IRQ_STATUS_DOU1))
evts |= get_dou_event(d71_pipeline);
return evts;
}
static irqreturn_t
d71_irq_handler(struct komeda_dev *mdev, struct komeda_events *evts)
{
struct d71_dev *d71 = mdev->chip_data;
u32 status, gcu_status, raw_status;
gcu_status = malidp_read32(d71->gcu_addr, GLB_IRQ_STATUS);
if (gcu_status & GLB_IRQ_STATUS_GCU) {
raw_status = malidp_read32(d71->gcu_addr, BLK_IRQ_RAW_STATUS);
if (raw_status & GCU_IRQ_CVAL0)
evts->pipes[0] |= KOMEDA_EVENT_FLIP;
if (raw_status & GCU_IRQ_CVAL1)
evts->pipes[1] |= KOMEDA_EVENT_FLIP;
if (raw_status & GCU_IRQ_ERR) {
status = malidp_read32(d71->gcu_addr, BLK_STATUS);
if (status & GCU_STATUS_MERR) {
evts->global |= KOMEDA_ERR_MERR;
malidp_write32_mask(d71->gcu_addr, BLK_STATUS,
GCU_STATUS_MERR, 0);
}
}
malidp_write32(d71->gcu_addr, BLK_IRQ_CLEAR, raw_status);
}
if (gcu_status & GLB_IRQ_STATUS_PIPE0)
evts->pipes[0] |= get_pipeline_event(d71->pipes[0], gcu_status);
if (gcu_status & GLB_IRQ_STATUS_PIPE1)
evts->pipes[1] |= get_pipeline_event(d71->pipes[1], gcu_status);
return gcu_status ? IRQ_HANDLED : IRQ_NONE;
}
#define ENABLED_GCU_IRQS (GCU_IRQ_CVAL0 | GCU_IRQ_CVAL1 | \
GCU_IRQ_MODE | GCU_IRQ_ERR)
#define ENABLED_LPU_IRQS (LPU_IRQ_IBSY | LPU_IRQ_ERR | LPU_IRQ_EOW)
#define ENABLED_CU_IRQS (CU_IRQ_OVR | CU_IRQ_ERR)
#define ENABLED_DOU_IRQS (DOU_IRQ_UND | DOU_IRQ_ERR)
static int d71_enable_irq(struct komeda_dev *mdev)
{
struct d71_dev *d71 = mdev->chip_data;
struct d71_pipeline *pipe;
u32 i;
malidp_write32_mask(d71->gcu_addr, BLK_IRQ_MASK,
ENABLED_GCU_IRQS, ENABLED_GCU_IRQS);
for (i = 0; i < d71->num_pipelines; i++) {
pipe = d71->pipes[i];
malidp_write32_mask(pipe->cu_addr, BLK_IRQ_MASK,
ENABLED_CU_IRQS, ENABLED_CU_IRQS);
malidp_write32_mask(pipe->lpu_addr, BLK_IRQ_MASK,
ENABLED_LPU_IRQS, ENABLED_LPU_IRQS);
malidp_write32_mask(pipe->dou_addr, BLK_IRQ_MASK,
ENABLED_DOU_IRQS, ENABLED_DOU_IRQS);
}
return 0;
}
static int d71_disable_irq(struct komeda_dev *mdev)
{
struct d71_dev *d71 = mdev->chip_data;
struct d71_pipeline *pipe;
u32 i;
malidp_write32_mask(d71->gcu_addr, BLK_IRQ_MASK, ENABLED_GCU_IRQS, 0);
for (i = 0; i < d71->num_pipelines; i++) {
pipe = d71->pipes[i];
malidp_write32_mask(pipe->cu_addr, BLK_IRQ_MASK,
ENABLED_CU_IRQS, 0);
malidp_write32_mask(pipe->lpu_addr, BLK_IRQ_MASK,
ENABLED_LPU_IRQS, 0);
malidp_write32_mask(pipe->dou_addr, BLK_IRQ_MASK,
ENABLED_DOU_IRQS, 0);
}
return 0;
}
static int d71_reset(struct d71_dev *d71)
{
u32 __iomem *gcu = d71->gcu_addr;
int ret;
malidp_write32_mask(gcu, BLK_CONTROL,
GCU_CONTROL_SRST, GCU_CONTROL_SRST);
ret = dp_wait_cond(!(malidp_read32(gcu, BLK_CONTROL) & GCU_CONTROL_SRST),
100, 1000, 10000);
return ret > 0 ? 0 : -ETIMEDOUT;
}
void d71_read_block_header(u32 __iomem *reg, struct block_header *blk)
{
int i;
blk->block_info = malidp_read32(reg, BLK_BLOCK_INFO);
if (BLOCK_INFO_BLK_TYPE(blk->block_info) == D71_BLK_TYPE_RESERVED)
return;
blk->pipeline_info = malidp_read32(reg, BLK_PIPELINE_INFO);
/* get valid input and output ids */
for (i = 0; i < PIPELINE_INFO_N_VALID_INPUTS(blk->pipeline_info); i++)
blk->input_ids[i] = malidp_read32(reg + i, BLK_VALID_INPUT_ID0);
for (i = 0; i < PIPELINE_INFO_N_OUTPUTS(blk->pipeline_info); i++)
blk->output_ids[i] = malidp_read32(reg + i, BLK_OUTPUT_ID0);
}
static void d71_cleanup(struct komeda_dev *mdev)
{
struct d71_dev *d71 = mdev->chip_data;
if (!d71)
return;
devm_kfree(mdev->dev, d71);
mdev->chip_data = NULL;
}
static int d71_enum_resources(struct komeda_dev *mdev)
{
/* TODO add enum resources */
return -1;
struct d71_dev *d71;
struct komeda_pipeline *pipe;
struct block_header blk;
u32 __iomem *blk_base;
u32 i, value, offset;
int err;
d71 = devm_kzalloc(mdev->dev, sizeof(*d71), GFP_KERNEL);
if (!d71)
return -ENOMEM;
mdev->chip_data = d71;
d71->mdev = mdev;
d71->gcu_addr = mdev->reg_base;
d71->periph_addr = mdev->reg_base + (D71_BLOCK_OFFSET_PERIPH >> 2);
err = d71_reset(d71);
if (err) {
DRM_ERROR("Fail to reset d71 device.\n");
goto err_cleanup;
}
/* probe GCU */
value = malidp_read32(d71->gcu_addr, GLB_CORE_INFO);
d71->num_blocks = value & 0xFF;
d71->num_pipelines = (value >> 8) & 0x7;
if (d71->num_pipelines > D71_MAX_PIPELINE) {
DRM_ERROR("d71 supports %d pipelines, but got: %d.\n",
D71_MAX_PIPELINE, d71->num_pipelines);
err = -EINVAL;
goto err_cleanup;
}
/* probe PERIPH */
value = malidp_read32(d71->periph_addr, BLK_BLOCK_INFO);
if (BLOCK_INFO_BLK_TYPE(value) != D71_BLK_TYPE_PERIPH) {
DRM_ERROR("access blk periph but got blk: %d.\n",
BLOCK_INFO_BLK_TYPE(value));
err = -EINVAL;
goto err_cleanup;
}
value = malidp_read32(d71->periph_addr, PERIPH_CONFIGURATION_ID);
d71->max_line_size = value & PERIPH_MAX_LINE_SIZE ? 4096 : 2048;
d71->max_vsize = 4096;
d71->num_rich_layers = value & PERIPH_NUM_RICH_LAYERS ? 2 : 1;
d71->supports_dual_link = value & PERIPH_SPLIT_EN ? true : false;
d71->integrates_tbu = value & PERIPH_TBU_EN ? true : false;
for (i = 0; i < d71->num_pipelines; i++) {
pipe = komeda_pipeline_add(mdev, sizeof(struct d71_pipeline),
NULL);
if (IS_ERR(pipe)) {
err = PTR_ERR(pipe);
goto err_cleanup;
}
d71->pipes[i] = to_d71_pipeline(pipe);
}
/* loop the register blks and probe */
i = 2; /* exclude GCU and PERIPH */
offset = D71_BLOCK_SIZE; /* skip GCU */
while (i < d71->num_blocks) {
blk_base = mdev->reg_base + (offset >> 2);
d71_read_block_header(blk_base, &blk);
if (BLOCK_INFO_BLK_TYPE(blk.block_info) != D71_BLK_TYPE_RESERVED) {
err = d71_probe_block(d71, &blk, blk_base);
if (err)
goto err_cleanup;
i++;
}
offset += D71_BLOCK_SIZE;
}
DRM_DEBUG("total %d (out of %d) blocks are found.\n",
i, d71->num_blocks);
return 0;
err_cleanup:
d71_cleanup(mdev);
return err;
}
#define __HW_ID(__group, __format) \
@ -93,13 +455,12 @@ static void d71_init_fmt_tbl(struct komeda_dev *mdev)
static struct komeda_dev_funcs d71_chip_funcs = {
.init_format_table = d71_init_fmt_tbl,
.enum_resources = d71_enum_resources,
.cleanup = NULL,
.cleanup = d71_cleanup,
.irq_handler = d71_irq_handler,
.enable_irq = d71_enable_irq,
.disable_irq = d71_disable_irq,
};
#define GLB_ARCH_ID 0x000
#define GLB_CORE_ID 0x004
#define GLB_CORE_INFO 0x008
struct komeda_dev_funcs *
d71_identify(u32 __iomem *reg_base, struct komeda_chip_info *chip)
{

50
drivers/gpu/drm/arm/display/komeda/d71/d71_dev.h Normal file
View File

@ -0,0 +1,50 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* (C) COPYRIGHT 2018 ARM Limited. All rights reserved.
* Author: James.Qian.Wang <james.qian.wang@arm.com>
*
*/
#ifndef _D71_DEV_H_
#define _D71_DEV_H_
#include "komeda_dev.h"
#include "komeda_pipeline.h"
#include "d71_regs.h"
struct d71_pipeline {
struct komeda_pipeline base;
/* d71 private pipeline blocks */
u32 __iomem *lpu_addr;
u32 __iomem *cu_addr;
u32 __iomem *dou_addr;
u32 __iomem *dou_ft_coeff_addr; /* forward transform coeffs table */
};
struct d71_dev {
struct komeda_dev *mdev;
int num_blocks;
int num_pipelines;
int num_rich_layers;
u32 max_line_size;
u32 max_vsize;
u32 supports_dual_link : 1;
u32 integrates_tbu : 1;
/* global register blocks */
u32 __iomem *gcu_addr;
/* scaling coeffs table */
u32 __iomem *glb_scl_coeff_addr[D71_MAX_GLB_SCL_COEFF];
u32 __iomem *periph_addr;
struct d71_pipeline *pipes[D71_MAX_PIPELINE];
};
#define to_d71_pipeline(x) container_of(x, struct d71_pipeline, base)
int d71_probe_block(struct d71_dev *d71,
struct block_header *blk, u32 __iomem *reg);
void d71_read_block_header(u32 __iomem *reg, struct block_header *blk);
#endif /* !_D71_DEV_H_ */

530
drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h Normal file
View File

@ -0,0 +1,530 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* (C) COPYRIGHT 2018 ARM Limited. All rights reserved.
* Author: James.Qian.Wang <james.qian.wang@arm.com>
*
*/
#ifndef _D71_REG_H_
#define _D71_REG_H_
/* Common block registers offset */
#define BLK_BLOCK_INFO 0x000
#define BLK_PIPELINE_INFO 0x004
#define BLK_VALID_INPUT_ID0 0x020
#define BLK_OUTPUT_ID0 0x060
#define BLK_INPUT_ID0 0x080
#define BLK_IRQ_RAW_STATUS 0x0A0
#define BLK_IRQ_CLEAR 0x0A4
#define BLK_IRQ_MASK 0x0A8
#define BLK_IRQ_STATUS 0x0AC
#define BLK_STATUS 0x0B0
#define BLK_INFO 0x0C0
#define BLK_CONTROL 0x0D0
#define BLK_SIZE 0x0D4
#define BLK_IN_SIZE 0x0E0
#define BLK_P0_PTR_LOW 0x100
#define BLK_P0_PTR_HIGH 0x104
#define BLK_P0_STRIDE 0x108
#define BLK_P1_PTR_LOW 0x110
#define BLK_P1_PTR_HIGH 0x114
#define BLK_P1_STRIDE 0x118
#define BLK_P2_PTR_LOW 0x120
#define BLK_P2_PTR_HIGH 0x124
#define BLOCK_INFO_N_SUBBLKS(x) ((x) & 0x000F)
#define BLOCK_INFO_BLK_ID(x) (((x) & 0x00F0) >> 4)
#define BLOCK_INFO_BLK_TYPE(x) (((x) & 0xFF00) >> 8)
#define BLOCK_INFO_INPUT_ID(x) ((x) & 0xFFF0)
#define BLOCK_INFO_TYPE_ID(x) (((x) & 0x0FF0) >> 4)
#define PIPELINE_INFO_N_OUTPUTS(x) ((x) & 0x000F)
#define PIPELINE_INFO_N_VALID_INPUTS(x) (((x) & 0x0F00) >> 8)
/* Common block control register bits */
#define BLK_CTRL_EN BIT(0)
/* Common size macro */
#define HV_SIZE(h, v) (((h) & 0x1FFF) + (((v) & 0x1FFF) << 16))
#define HV_OFFSET(h, v) (((h) & 0xFFF) + (((v) & 0xFFF) << 16))
#define HV_CROP(h, v) (((h) & 0xFFF) + (((v) & 0xFFF) << 16))
/* AD_CONTROL register */
#define AD_CONTROL 0x160
/* AD_CONTROL register bits */
#define AD_AEN BIT(0)
#define AD_YT BIT(1)
#define AD_BS BIT(2)
#define AD_WB BIT(3)
#define AD_TH BIT(4)
/* Global Control Unit */
#define GLB_ARCH_ID 0x000
#define GLB_CORE_ID 0x004
#define GLB_CORE_INFO 0x008
#define GLB_IRQ_STATUS 0x010
#define GCU_CONFIG_VALID0 0x0D4
#define GCU_CONFIG_VALID1 0x0D8
/* GCU_CONTROL_BITS */
#define GCU_CONTROL_MODE(x) ((x) & 0x7)
#define GCU_CONTROL_SRST BIT(16)
/* GCU opmode */
#define INACTIVE_MODE 0
#define TBU_CONNECT_MODE 1
#define TBU_DISCONNECT_MODE 2
#define DO0_ACTIVE_MODE 3
#define DO1_ACTIVE_MODE 4
#define DO01_ACTIVE_MODE 5
/* GLB_IRQ_STATUS bits */
#define GLB_IRQ_STATUS_GCU BIT(0)
#define GLB_IRQ_STATUS_LPU0 BIT(8)
#define GLB_IRQ_STATUS_LPU1 BIT(9)
#define GLB_IRQ_STATUS_ATU0 BIT(10)
#define GLB_IRQ_STATUS_ATU1 BIT(11)
#define GLB_IRQ_STATUS_ATU2 BIT(12)
#define GLB_IRQ_STATUS_ATU3 BIT(13)
#define GLB_IRQ_STATUS_CU0 BIT(16)
#define GLB_IRQ_STATUS_CU1 BIT(17)
#define GLB_IRQ_STATUS_DOU0 BIT(24)
#define GLB_IRQ_STATUS_DOU1 BIT(25)
#define GLB_IRQ_STATUS_PIPE0 (GLB_IRQ_STATUS_LPU0 |\
GLB_IRQ_STATUS_ATU0 |\
GLB_IRQ_STATUS_ATU1 |\
GLB_IRQ_STATUS_CU0 |\
GLB_IRQ_STATUS_DOU0)
#define GLB_IRQ_STATUS_PIPE1 (GLB_IRQ_STATUS_LPU1 |\
GLB_IRQ_STATUS_ATU2 |\
GLB_IRQ_STATUS_ATU3 |\
GLB_IRQ_STATUS_CU1 |\
GLB_IRQ_STATUS_DOU1)
#define GLB_IRQ_STATUS_ATU (GLB_IRQ_STATUS_ATU0 |\
GLB_IRQ_STATUS_ATU1 |\
GLB_IRQ_STATUS_ATU2 |\
GLB_IRQ_STATUS_ATU3)
/* GCU_IRQ_BITS */
#define GCU_IRQ_CVAL0 BIT(0)
#define GCU_IRQ_CVAL1 BIT(1)
#define GCU_IRQ_MODE BIT(4)
#define GCU_IRQ_ERR BIT(11)
/* GCU_STATUS_BITS */
#define GCU_STATUS_MODE(x) ((x) & 0x7)
#define GCU_STATUS_MERR BIT(4)
#define GCU_STATUS_TCS0 BIT(8)
#define GCU_STATUS_TCS1 BIT(9)
#define GCU_STATUS_ACTIVE BIT(31)
/* GCU_CONFIG_VALIDx BITS */
#define GCU_CONFIG_CVAL BIT(0)
/* PERIPHERAL registers */
#define PERIPH_MAX_LINE_SIZE BIT(0)
#define PERIPH_NUM_RICH_LAYERS BIT(4)
#define PERIPH_SPLIT_EN BIT(8)
#define PERIPH_TBU_EN BIT(12)
#define PERIPH_AFBC_DMA_EN BIT(16)
#define PERIPH_CONFIGURATION_ID 0x1D4
/* LPU register */
#define LPU_TBU_STATUS 0x0B4
#define LPU_RAXI_CONTROL 0x0D0
#define LPU_WAXI_CONTROL 0x0D4
#define LPU_TBU_CONTROL 0x0D8
/* LPU_xAXI_CONTROL_BITS */
#define TO_RAXI_AOUTSTDCAPB(x) (x)
#define TO_RAXI_BOUTSTDCAPB(x) ((x) << 8)
#define TO_RAXI_BEN(x) ((x) << 15)
#define TO_xAXI_BURSTLEN(x) ((x) << 16)
#define TO_xAXI_AxQOS(x) ((x) << 24)
#define TO_xAXI_ORD(x) ((x) << 31)
#define TO_WAXI_OUTSTDCAPB(x) (x)
#define RAXI_AOUTSTDCAPB_MASK 0x7F
#define RAXI_BOUTSTDCAPB_MASK 0x7F00
#define RAXI_BEN_MASK BIT(15)
#define xAXI_BURSTLEN_MASK 0x3F0000
#define xAXI_AxQOS_MASK 0xF000000
#define xAXI_ORD_MASK BIT(31)
#define WAXI_OUTSTDCAPB_MASK 0x3F
/* LPU_TBU_CONTROL BITS */
#define TO_TBU_DOUTSTDCAPB(x) (x)
#define TBU_DOUTSTDCAPB_MASK 0x3F
/* LPU_IRQ_BITS */
#define LPU_IRQ_IBSY BIT(10)
#define LPU_IRQ_ERR BIT(11)
#define LPU_IRQ_EOW BIT(12)
#define LPU_IRQ_PL0 BIT(13)
/* LPU_STATUS_BITS */
#define LPU_STATUS_AXIED(x) ((x) & 0xF)
#define LPU_STATUS_AXIE BIT(4)
#define LPU_STATUS_AXIRP BIT(5)
#define LPU_STATUS_AXIWP BIT(6)
#define LPU_STATUS_ACE0 BIT(16)
#define LPU_STATUS_ACE1 BIT(17)
#define LPU_STATUS_ACE2 BIT(18)
#define LPU_STATUS_ACE3 BIT(19)
#define LPU_STATUS_ACTIVE BIT(31)
#define AXIEID_MASK 0xF
#define AXIE_MASK LPU_STATUS_AXIE
#define AXIRP_MASK LPU_STATUS_AXIRP
#define AXIWP_MASK LPU_STATUS_AXIWP
#define FROM_AXIEID(reg) ((reg) & AXIEID_MASK)
#define TO_AXIE(x) ((x) << 4)
#define FROM_AXIRP(reg) (((reg) & AXIRP_MASK) >> 5)
#define FROM_AXIWP(reg) (((reg) & AXIWP_MASK) >> 6)
/* LPU_TBU_STATUS_BITS */
#define LPU_TBU_STATUS_TCF BIT(1)
#define LPU_TBU_STATUS_TTNG BIT(2)
#define LPU_TBU_STATUS_TITR BIT(8)
#define LPU_TBU_STATUS_TEMR BIT(16)
#define LPU_TBU_STATUS_TTF BIT(31)
/* LPU_TBU_CONTROL BITS */
#define LPU_TBU_CTRL_TLBPEN BIT(16)
/* CROSSBAR CONTROL BITS */
#define CBU_INPUT_CTRL_EN BIT(0)
#define CBU_NUM_INPUT_IDS 5
#define CBU_NUM_OUTPUT_IDS 5
/* CU register */
#define CU_BG_COLOR 0x0DC
#define CU_INPUT0_SIZE 0x0E0
#define CU_INPUT0_OFFSET 0x0E4
#define CU_INPUT0_CONTROL 0x0E8
#define CU_INPUT1_SIZE 0x0F0
#define CU_INPUT1_OFFSET 0x0F4
#define CU_INPUT1_CONTROL 0x0F8
#define CU_INPUT2_SIZE 0x100
#define CU_INPUT2_OFFSET 0x104
#define CU_INPUT2_CONTROL 0x108
#define CU_INPUT3_SIZE 0x110
#define CU_INPUT3_OFFSET 0x114
#define CU_INPUT3_CONTROL 0x118
#define CU_INPUT4_SIZE 0x120
#define CU_INPUT4_OFFSET 0x124
#define CU_INPUT4_CONTROL 0x128
#define CU_PER_INPUT_REGS 4
#define CU_NUM_INPUT_IDS 5
#define CU_NUM_OUTPUT_IDS 1
/* CU control register bits */
#define CU_CTRL_COPROC BIT(0)
/* CU_IRQ_BITS */
#define CU_IRQ_OVR BIT(9)
#define CU_IRQ_ERR BIT(11)
/* CU_STATUS_BITS */
#define CU_STATUS_CPE BIT(0)
#define CU_STATUS_ZME BIT(1)
#define CU_STATUS_CFGE BIT(2)
#define CU_STATUS_ACTIVE BIT(31)
/* CU input control register bits */
#define CU_INPUT_CTRL_EN BIT(0)
#define CU_INPUT_CTRL_PAD BIT(1)
#define CU_INPUT_CTRL_PMUL BIT(2)
#define CU_INPUT_CTRL_ALPHA(x) (((x) & 0xFF) << 8)
/* DOU register */
/* DOU_IRQ_BITS */
#define DOU_IRQ_UND BIT(8)
#define DOU_IRQ_ERR BIT(11)
#define DOU_IRQ_PL0 BIT(13)
#define DOU_IRQ_PL1 BIT(14)
/* DOU_STATUS_BITS */
#define DOU_STATUS_DRIFTTO BIT(0)
#define DOU_STATUS_FRAMETO BIT(1)
#define DOU_STATUS_TETO BIT(2)
#define DOU_STATUS_CSCE BIT(8)
#define DOU_STATUS_ACTIVE BIT(31)
/* Layer registers */
#define LAYER_INFO 0x0C0
#define LAYER_R_CONTROL 0x0D4
#define LAYER_FMT 0x0D8
#define LAYER_LT_COEFFTAB 0x0DC
#define LAYER_PALPHA 0x0E4
#define LAYER_YUV_RGB_COEFF0 0x130
#define LAYER_AD_H_CROP 0x164
#define LAYER_AD_V_CROP 0x168
#define LAYER_RGB_RGB_COEFF0 0x170
/* L_CONTROL_BITS */
#define L_EN BIT(0)
#define L_IT BIT(4)
#define L_R2R BIT(5)
#define L_FT BIT(6)
#define L_ROT(x) (((x) & 3) << 8)
#define L_HFLIP BIT(10)
#define L_VFLIP BIT(11)
#define L_TBU_EN BIT(16)
#define L_A_RCACHE(x) (((x) & 0xF) << 28)
#define L_ROT_R0 0
#define L_ROT_R90 1
#define L_ROT_R180 2
#define L_ROT_R270 3
/* LAYER_R_CONTROL BITS */
#define LR_CHI422_BILINEAR 0
#define LR_CHI422_REPLICATION 1
#define LR_CHI420_JPEG (0 << 2)
#define LR_CHI420_MPEG (1 << 2)
#define L_ITSEL(x) ((x) & 0xFFF)
#define L_FTSEL(x) (((x) & 0xFFF) << 16)
#define LAYER_PER_PLANE_REGS 4
/* Layer_WR registers */
#define LAYER_WR_PROG_LINE 0x0D4
#define LAYER_WR_FORMAT 0x0D8
/* Layer_WR control bits */
#define LW_OFM BIT(4)
#define LW_LALPHA(x) (((x) & 0xFF) << 8)
#define LW_A_WCACHE(x) (((x) & 0xF) << 28)
#define LW_TBU_EN BIT(16)
#define AxCACHE_MASK 0xF0000000
/* Layer AXI R/W cache setting */
#define AxCACHE_B BIT(0) /* Bufferable */
#define AxCACHE_M BIT(1) /* Modifiable */
#define AxCACHE_RA BIT(2) /* Read-Allocate */
#define AxCACHE_WA BIT(3) /* Write-Allocate */
/* Layer info bits */
#define L_INFO_RF BIT(0)
#define L_INFO_CM BIT(1)
#define L_INFO_ABUF_SIZE(x) (((x) >> 4) & 0x7)
/* Scaler registers */
#define SC_COEFFTAB 0x0DC
#define SC_OUT_SIZE 0x0E4
#define SC_H_CROP 0x0E8
#define SC_V_CROP 0x0EC
#define SC_H_INIT_PH 0x0F0
#define SC_H_DELTA_PH 0x0F4
#define SC_V_INIT_PH 0x0F8
#define SC_V_DELTA_PH 0x0FC
#define SC_ENH_LIMITS 0x130
#define SC_ENH_COEFF0 0x134
#define SC_MAX_ENH_COEFF 9
/* SC_CTRL_BITS */
#define SC_CTRL_SCL BIT(0)
#define SC_CTRL_LS BIT(1)
#define SC_CTRL_AP BIT(4)
#define SC_CTRL_IENH BIT(8)
#define SC_CTRL_RGBSM BIT(16)
#define SC_CTRL_ASM BIT(17)
#define SC_VTSEL(vtal) ((vtal) << 16)
#define SC_NUM_INPUTS_IDS 1
#define SC_NUM_OUTPUTS_IDS 1
#define MG_NUM_INPUTS_IDS 2
#define MG_NUM_OUTPUTS_IDS 1
/* Merger registers */
#define MG_INPUT_ID0 BLK_INPUT_ID0
#define MG_INPUT_ID1 (MG_INPUT_ID0 + 4)
#define MG_SIZE BLK_SIZE
/* Splitter registers */
#define SP_OVERLAP_SIZE 0xD8
/* Backend registers */
#define BS_INFO 0x0C0
#define BS_PROG_LINE 0x0D4
#define BS_PREFETCH_LINE 0x0D8
#define BS_BG_COLOR 0x0DC
#define BS_ACTIVESIZE 0x0E0
#define BS_HINTERVALS 0x0E4
#define BS_VINTERVALS 0x0E8
#define BS_SYNC 0x0EC
#define BS_DRIFT_TO 0x100
#define BS_FRAME_TO 0x104
#define BS_TE_TO 0x108
#define BS_T0_INTERVAL 0x110
#define BS_T1_INTERVAL 0x114
#define BS_T2_INTERVAL 0x118
#define BS_CRC0_LOW 0x120
#define BS_CRC0_HIGH 0x124
#define BS_CRC1_LOW 0x128
#define BS_CRC1_HIGH 0x12C
#define BS_USER 0x130
/* BS control register bits */
#define BS_CTRL_EN BIT(0)
#define BS_CTRL_VM BIT(1)
#define BS_CTRL_BM BIT(2)
#define BS_CTRL_HMASK BIT(4)
#define BS_CTRL_VD BIT(5)
#define BS_CTRL_TE BIT(8)
#define BS_CTRL_TS BIT(9)
#define BS_CTRL_TM BIT(12)
#define BS_CTRL_DL BIT(16)
#define BS_CTRL_SBS BIT(17)
#define BS_CTRL_CRC BIT(18)
#define BS_CTRL_PM BIT(20)
/* BS active size/intervals */
#define BS_H_INTVALS(hfp, hbp) (((hfp) & 0xFFF) + (((hbp) & 0x3FF) << 16))
#define BS_V_INTVALS(vfp, vbp) (((vfp) & 0x3FFF) + (((vbp) & 0xFF) << 16))
/* BS_SYNC bits */
#define BS_SYNC_HSW(x) ((x) & 0x3FF)
#define BS_SYNC_HSP BIT(12)
#define BS_SYNC_VSW(x) (((x) & 0xFF) << 16)
#define BS_SYNC_VSP BIT(28)
#define BS_NUM_INPUT_IDS 0
#define BS_NUM_OUTPUT_IDS 0
/* Image process registers */
#define IPS_DEPTH 0x0D8
#define IPS_RGB_RGB_COEFF0 0x130
#define IPS_RGB_YUV_COEFF0 0x170
#define IPS_DEPTH_MARK 0xF
/* IPS control register bits */
#define IPS_CTRL_RGB BIT(0)
#define IPS_CTRL_FT BIT(4)
#define IPS_CTRL_YUV BIT(8)
#define IPS_CTRL_CHD422 BIT(9)
#define IPS_CTRL_CHD420 BIT(10)
#define IPS_CTRL_LPF BIT(11)
#define IPS_CTRL_DITH BIT(12)
#define IPS_CTRL_CLAMP BIT(16)
#define IPS_CTRL_SBS BIT(17)
/* IPS info register bits */
#define IPS_INFO_CHD420 BIT(10)
#define IPS_NUM_INPUT_IDS 2
#define IPS_NUM_OUTPUT_IDS 1
/* FT_COEFF block registers */
#define FT_COEFF0 0x80
#define GLB_IT_COEFF 0x80
/* GLB_SC_COEFF registers */
#define GLB_SC_COEFF_ADDR 0x0080
#define GLB_SC_COEFF_DATA 0x0084
#define GLB_LT_COEFF_DATA 0x0080
#define GLB_SC_COEFF_MAX_NUM 1024
#define GLB_LT_COEFF_NUM 65
/* GLB_SC_ADDR */
#define SC_COEFF_R_ADDR BIT(18)
#define SC_COEFF_G_ADDR BIT(17)
#define SC_COEFF_B_ADDR BIT(16)
#define SC_COEFF_DATA(x, y) (((y) & 0xFFFF) | (((x) & 0xFFFF) << 16))
enum d71_blk_type {
D71_BLK_TYPE_GCU = 0x00,
D71_BLK_TYPE_LPU = 0x01,
D71_BLK_TYPE_CU = 0x02,
D71_BLK_TYPE_DOU = 0x03,
D71_BLK_TYPE_AEU = 0x04,
D71_BLK_TYPE_GLB_LT_COEFF = 0x05,
D71_BLK_TYPE_GLB_SCL_COEFF = 0x06, /* SH/SV scaler coeff */
D71_BLK_TYPE_GLB_SC_COEFF = 0x07,
D71_BLK_TYPE_PERIPH = 0x08,
D71_BLK_TYPE_LPU_TRUSTED = 0x09,
D71_BLK_TYPE_AEU_TRUSTED = 0x0A,
D71_BLK_TYPE_LPU_LAYER = 0x10,
D71_BLK_TYPE_LPU_WB_LAYER = 0x11,
D71_BLK_TYPE_CU_SPLITTER = 0x20,
D71_BLK_TYPE_CU_SCALER = 0x21,
D71_BLK_TYPE_CU_MERGER = 0x22,
D71_BLK_TYPE_DOU_IPS = 0x30,
D71_BLK_TYPE_DOU_BS = 0x31,
D71_BLK_TYPE_DOU_FT_COEFF = 0x32,
D71_BLK_TYPE_AEU_DS = 0x40,
D71_BLK_TYPE_AEU_AES = 0x41,
D71_BLK_TYPE_RESERVED = 0xFF
};
/* Constant of components */
#define D71_MAX_PIPELINE 2
#define D71_PIPELINE_MAX_SCALERS 2
#define D71_PIPELINE_MAX_LAYERS 4
#define D71_MAX_GLB_IT_COEFF 3
#define D71_MAX_GLB_SCL_COEFF 4
#define D71_MAX_LAYERS_PER_LPU 4
#define D71_BLOCK_MAX_INPUT 9
#define D71_BLOCK_MAX_OUTPUT 5
#define D71_MAX_SC_PER_CU 2
#define D71_BLOCK_OFFSET_PERIPH 0xFE00
#define D71_BLOCK_SIZE 0x0200
#define D71_DEFAULT_PREPRETCH_LINE 5
#define D71_BUS_WIDTH_16_BYTES 16
#define D71_MIN_LINE_SIZE 64
#define D71_MIN_VERTICAL_SIZE 64
#define D71_SC_MIN_LIN_SIZE 4
#define D71_SC_MIN_VERTICAL_SIZE 4
#define D71_SC_MAX_LIN_SIZE 2048
#define D71_SC_MAX_VERTICAL_SIZE 4096
#define D71_SC_MAX_UPSCALING 64
#define D71_SC_MAX_DOWNSCALING 6
#define D71_SC_SPLIT_OVERLAP 8
#define D71_SC_ENH_SPLIT_OVERLAP 1
#define D71_MG_MIN_MERGED_SIZE 4
#define D71_MG_MAX_MERGED_HSIZE 4032
#define D71_MG_MAX_MERGED_VSIZE 4096
#define D71_PALPHA_DEF_MAP 0xFFAA5500
#define D71_LAYER_CONTROL_DEFAULT 0x30000000
#define D71_WB_LAYER_CONTROL_DEFAULT 0x3000FF00
#define D71_BS_CONTROL_DEFAULT 0x00000002
struct block_header {
u32 block_info;
u32 pipeline_info;
u32 input_ids[D71_BLOCK_MAX_INPUT];
u32 output_ids[D71_BLOCK_MAX_OUTPUT];
};
static inline u32 get_block_type(struct block_header *blk)
{
return BLOCK_INFO_BLK_TYPE(blk->block_info);
}
#endif /* !_D71_REG_H_ */

18
drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
View File

@ -18,6 +18,24 @@
#include "komeda_dev.h"
#include "komeda_kms.h"
void komeda_crtc_handle_event(struct komeda_crtc *kcrtc,
struct komeda_events *evts)
{
struct drm_crtc *crtc = &kcrtc->base;
u32 events = evts->pipes[kcrtc->master->id];
if (events & KOMEDA_EVENT_VSYNC)
drm_crtc_handle_vblank(crtc);
/* will handle it together with the write back support */
if (events & KOMEDA_EVENT_EOW)
DRM_DEBUG("EOW.\n");
/* will handle it with crtc->flush */
if (events & KOMEDA_EVENT_FLIP)
DRM_DEBUG("FLIP Done.\n");
}
struct drm_crtc_helper_funcs komeda_crtc_helper_funcs = {
};

66
drivers/gpu/drm/arm/display/komeda/komeda_dev.c
View File

@ -8,11 +8,57 @@
#include <linux/of_device.h>
#include <linux/of_graph.h>
#include <linux/platform_device.h>
#ifdef CONFIG_DEBUG_FS
#include <linux/debugfs.h>
#include <linux/seq_file.h>
#endif
#include <drm/drm_print.h>
#include "komeda_dev.h"
static int komeda_register_show(struct seq_file *sf, void *x)
{
struct komeda_dev *mdev = sf->private;
int i;
if (mdev->funcs->dump_register)
mdev->funcs->dump_register(mdev, sf);
for (i = 0; i < mdev->n_pipelines; i++)
komeda_pipeline_dump_register(mdev->pipelines[i], sf);
return 0;
}
static int komeda_register_open(struct inode *inode, struct file *filp)
{
return single_open(filp, komeda_register_show, inode->i_private);
}
static const struct file_operations komeda_register_fops = {
.owner = THIS_MODULE,
.open = komeda_register_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
#ifdef CONFIG_DEBUG_FS
static void komeda_debugfs_init(struct komeda_dev *mdev)
{
if (!debugfs_initialized())
return;
mdev->debugfs_root = debugfs_create_dir("komeda", NULL);
if (IS_ERR_OR_NULL(mdev->debugfs_root))
return;
debugfs_create_file("register", 0444, mdev->debugfs_root,
mdev, &komeda_register_fops);
}
#endif
static int komeda_parse_pipe_dt(struct komeda_dev *mdev, struct device_node *np)
{
struct komeda_pipeline *pipe;
@ -53,6 +99,7 @@ static int komeda_parse_pipe_dt(struct komeda_dev *mdev, struct device_node *np)
static int komeda_parse_dt(struct device *dev, struct komeda_dev *mdev)
{
struct platform_device *pdev = to_platform_device(dev);
struct device_node *child, *np = dev->of_node;
struct clk *clk;
int ret;
@ -62,6 +109,11 @@ static int komeda_parse_dt(struct device *dev, struct komeda_dev *mdev)
return PTR_ERR(clk);
mdev->mclk = clk;
mdev->irq = platform_get_irq(pdev, 0);
if (mdev->irq < 0) {
DRM_ERROR("could not get IRQ number.\n");
return mdev->irq;
}
for_each_available_child_of_node(np, child) {
if (of_node_cmp(child->name, "pipeline") == 0) {
@ -147,6 +199,16 @@ struct komeda_dev *komeda_dev_create(struct device *dev)
goto err_cleanup;
}
err = komeda_assemble_pipelines(mdev);
if (err) {
DRM_ERROR("assemble display pipelines failed.\n");
goto err_cleanup;
}
#ifdef CONFIG_DEBUG_FS
komeda_debugfs_init(mdev);
#endif
return mdev;
err_cleanup:
@ -160,6 +222,10 @@ void komeda_dev_destroy(struct komeda_dev *mdev)
struct komeda_dev_funcs *funcs = mdev->funcs;
int i;
#ifdef CONFIG_DEBUG_FS
debugfs_remove_recursive(mdev->debugfs_root);
#endif
for (i = 0; i < mdev->n_pipelines; i++) {
komeda_pipeline_destroy(mdev, mdev->pipelines[i]);
mdev->pipelines[i] = NULL;

51
drivers/gpu/drm/arm/display/komeda/komeda_dev.h
View File

@ -13,6 +13,33 @@
#include "malidp_product.h"
#include "komeda_format_caps.h"
#define KOMEDA_EVENT_VSYNC BIT_ULL(0)
#define KOMEDA_EVENT_FLIP BIT_ULL(1)
#define KOMEDA_EVENT_URUN BIT_ULL(2)
#define KOMEDA_EVENT_IBSY BIT_ULL(3)
#define KOMEDA_EVENT_OVR BIT_ULL(4)
#define KOMEDA_EVENT_EOW BIT_ULL(5)
#define KOMEDA_EVENT_MODE BIT_ULL(6)
#define KOMEDA_ERR_TETO BIT_ULL(14)
#define KOMEDA_ERR_TEMR BIT_ULL(15)
#define KOMEDA_ERR_TITR BIT_ULL(16)
#define KOMEDA_ERR_CPE BIT_ULL(17)
#define KOMEDA_ERR_CFGE BIT_ULL(18)
#define KOMEDA_ERR_AXIE BIT_ULL(19)
#define KOMEDA_ERR_ACE0 BIT_ULL(20)
#define KOMEDA_ERR_ACE1 BIT_ULL(21)
#define KOMEDA_ERR_ACE2 BIT_ULL(22)
#define KOMEDA_ERR_ACE3 BIT_ULL(23)
#define KOMEDA_ERR_DRIFTTO BIT_ULL(24)
#define KOMEDA_ERR_FRAMETO BIT_ULL(25)
#define KOMEDA_ERR_CSCE BIT_ULL(26)
#define KOMEDA_ERR_ZME BIT_ULL(27)
#define KOMEDA_ERR_MERR BIT_ULL(28)
#define KOMEDA_ERR_TCF BIT_ULL(29)
#define KOMEDA_ERR_TTNG BIT_ULL(30)
#define KOMEDA_ERR_TTF BIT_ULL(31)
/* malidp device id */
enum {
MALI_D71 = 0,
@ -39,6 +66,11 @@ struct komeda_product_data {
struct komeda_dev;
struct komeda_events {
u64 global;
u64 pipes[KOMEDA_MAX_PIPELINES];
};
/**
* struct komeda_dev_funcs
*
@ -60,6 +92,20 @@ struct komeda_dev_funcs {
int (*enum_resources)(struct komeda_dev *mdev);
/** @cleanup: call to chip to cleanup komeda_dev->chip data */
void (*cleanup)(struct komeda_dev *mdev);
/**
* @irq_handler:
*
* for CORE to get the HW event from the CHIP when interrupt happened.
*/
irqreturn_t (*irq_handler)(struct komeda_dev *mdev,
struct komeda_events *events);
/** @enable_irq: enable irq */
int (*enable_irq)(struct komeda_dev *mdev);
/** @disable_irq: disable irq */
int (*disable_irq)(struct komeda_dev *mdev);
/** @dump_register: Optional, dump registers to seq_file */
void (*dump_register)(struct komeda_dev *mdev, struct seq_file *seq);
};
/**
@ -81,6 +127,9 @@ struct komeda_dev {
/** @mck: HW main engine clk */
struct clk *mclk;
/** @irq: irq number */
int irq;
int n_pipelines;
struct komeda_pipeline *pipelines[KOMEDA_MAX_PIPELINES];
@ -93,6 +142,8 @@ struct komeda_dev {
* destroyed by &komeda_dev_funcs.cleanup()
*/
void *chip_data;
struct dentry *debugfs_root;
};
static inline bool

38
drivers/gpu/drm/arm/display/komeda/komeda_kms.c
View File

@ -13,6 +13,7 @@
#include <drm/drm_fb_helper.h>
#include <drm/drm_gem_cma_helper.h>
#include <drm/drm_gem_framebuffer_helper.h>
#include <drm/drm_irq.h>
#include <drm/drm_vblank.h>
#include "komeda_dev.h"
@ -33,10 +34,31 @@ static int komeda_gem_cma_dumb_create(struct drm_file *file,
return drm_gem_cma_dumb_create_internal(file, dev, args);
}
static irqreturn_t komeda_kms_irq_handler(int irq, void *data)
{
struct drm_device *drm = data;
struct komeda_dev *mdev = drm->dev_private;
struct komeda_kms_dev *kms = to_kdev(drm);
struct komeda_events evts;
irqreturn_t status;
u32 i;
/* Call into the CHIP to recognize events */
memset(&evts, 0, sizeof(evts));
status = mdev->funcs->irq_handler(mdev, &evts);
/* Notify the crtc to handle the events */
for (i = 0; i < kms->n_crtcs; i++)
komeda_crtc_handle_event(&kms->crtcs[i], &evts);
return status;
}
static struct drm_driver komeda_kms_driver = {
.driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC |
DRIVER_PRIME,
DRIVER_PRIME | DRIVER_HAVE_IRQ,
.lastclose = drm_fb_helper_lastclose,
.irq_handler = komeda_kms_irq_handler,
.gem_free_object_unlocked = drm_gem_cma_free_object,
.gem_vm_ops = &drm_gem_cma_vm_ops,
.dumb_create = komeda_gem_cma_dumb_create,
@ -144,12 +166,22 @@ struct komeda_kms_dev *komeda_kms_attach(struct komeda_dev *mdev)
drm_mode_config_reset(drm);
err = drm_dev_register(drm, 0);
err = drm_irq_install(drm, mdev->irq);
if (err)
goto cleanup_mode_config;
err = mdev->funcs->enable_irq(mdev);
if (err)
goto uninstall_irq;
err = drm_dev_register(drm, 0);
if (err)
goto uninstall_irq;
return kms;
uninstall_irq:
drm_irq_uninstall(drm);
cleanup_mode_config:
drm_mode_config_cleanup(drm);
free_kms:
@ -162,7 +194,9 @@ void komeda_kms_detach(struct komeda_kms_dev *kms)
struct drm_device *drm = &kms->base;
struct komeda_dev *mdev = drm->dev_private;
mdev->funcs->disable_irq(mdev);
drm_dev_unregister(drm);
drm_irq_uninstall(drm);
component_unbind_all(mdev->dev, drm);
komeda_kms_cleanup_private_objs(mdev);
drm_mode_config_cleanup(drm);

5
drivers/gpu/drm/arm/display/komeda/komeda_kms.h
View File

@ -12,6 +12,8 @@
#include <drm/drm_crtc_helper.h>
#include <drm/drm_device.h>
#include <drm/drm_writeback.h>
#include <video/videomode.h>
#include <video/display_timing.h>
/** struct komeda_plane - komeda instance of drm_plane */
struct komeda_plane {
@ -108,6 +110,9 @@ int komeda_kms_add_private_objs(struct komeda_kms_dev *kms,
struct komeda_dev *mdev);
void komeda_kms_cleanup_private_objs(struct komeda_dev *mdev);
void komeda_crtc_handle_event(struct komeda_crtc *kcrtc,
struct komeda_events *evts);
struct komeda_kms_dev *komeda_kms_attach(struct komeda_dev *mdev);
void komeda_kms_detach(struct komeda_kms_dev *kms);

111
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c
View File

@ -19,17 +19,17 @@ komeda_pipeline_add(struct komeda_dev *mdev, size_t size,
if (mdev->n_pipelines + 1 > KOMEDA_MAX_PIPELINES) {
DRM_ERROR("Exceed max support %d pipelines.\n",
KOMEDA_MAX_PIPELINES);
return NULL;
return ERR_PTR(-ENOSPC);
}
if (size < sizeof(*pipe)) {
DRM_ERROR("Request pipeline size too small.\n");
return NULL;
return ERR_PTR(-EINVAL);
}
pipe = devm_kzalloc(mdev->dev, size, GFP_KERNEL);
if (!pipe)
return NULL;
return ERR_PTR(-ENOMEM);
pipe->mdev = mdev;
pipe->id = mdev->n_pipelines;
@ -142,32 +142,32 @@ komeda_component_add(struct komeda_pipeline *pipe,
if (max_active_inputs > KOMEDA_COMPONENT_N_INPUTS) {
WARN(1, "please large KOMEDA_COMPONENT_N_INPUTS to %d.\n",
max_active_inputs);
return NULL;
return ERR_PTR(-ENOSPC);
}
pos = komeda_pipeline_get_component_pos(pipe, id);
if (!pos || (*pos))
return NULL;
return ERR_PTR(-EINVAL);
if (has_bit(id, KOMEDA_PIPELINE_LAYERS)) {
idx = id - KOMEDA_COMPONENT_LAYER0;
num = &pipe->n_layers;
if (idx != pipe->n_layers) {
DRM_ERROR("please add Layer by id sequence.\n");
return NULL;
return ERR_PTR(-EINVAL);
}
} else if (has_bit(id, KOMEDA_PIPELINE_SCALERS)) {
idx = id - KOMEDA_COMPONENT_SCALER0;
num = &pipe->n_scalers;
if (idx != pipe->n_scalers) {
DRM_ERROR("please add Scaler by id sequence.\n");
return NULL;
return ERR_PTR(-EINVAL);
}
}
c = devm_kzalloc(pipe->mdev->dev, comp_sz, GFP_KERNEL);
if (!c)
return NULL;
return ERR_PTR(-ENOMEM);
c->id = id;
c->hw_id = hw_id;
@ -200,3 +200,98 @@ void komeda_component_destroy(struct komeda_dev *mdev,
{
devm_kfree(mdev->dev, c);
}
static void komeda_component_dump(struct komeda_component *c)
{
if (!c)
return;
DRM_DEBUG(" %s: ID %d-0x%08lx.\n",
c->name, c->id, BIT(c->id));
DRM_DEBUG(" max_active_inputs:%d, supported_inputs: 0x%08x.\n",
c->max_active_inputs, c->supported_inputs);
DRM_DEBUG(" max_active_outputs:%d, supported_outputs: 0x%08x.\n",
c->max_active_outputs, c->supported_outputs);
}
static void komeda_pipeline_dump(struct komeda_pipeline *pipe)
{
struct komeda_component *c;
int id;
DRM_INFO("Pipeline-%d: n_layers: %d, n_scalers: %d, output: %s\n",
pipe->id, pipe->n_layers, pipe->n_scalers,
pipe->of_output_dev ? pipe->of_output_dev->full_name : "none");
dp_for_each_set_bit(id, pipe->avail_comps) {
c = komeda_pipeline_get_component(pipe, id);
komeda_component_dump(c);
}
}
static void komeda_component_verify_inputs(struct komeda_component *c)
{
struct komeda_pipeline *pipe = c->pipeline;
struct komeda_component *input;
int id;
dp_for_each_set_bit(id, c->supported_inputs) {
input = komeda_pipeline_get_component(pipe, id);
if (!input) {
c->supported_inputs &= ~(BIT(id));
DRM_WARN("Can not find input(ID-%d) for component: %s.\n",
id, c->name);
continue;
}
input->supported_outputs |= BIT(c->id);
}
}
static void komeda_pipeline_assemble(struct komeda_pipeline *pipe)
{
struct komeda_component *c;
int id;
dp_for_each_set_bit(id, pipe->avail_comps) {
c = komeda_pipeline_get_component(pipe, id);
komeda_component_verify_inputs(c);
}
}
int komeda_assemble_pipelines(struct komeda_dev *mdev)
{
struct komeda_pipeline *pipe;
int i;
for (i = 0; i < mdev->n_pipelines; i++) {
pipe = mdev->pipelines[i];
komeda_pipeline_assemble(pipe);
komeda_pipeline_dump(pipe);
}
return 0;
}
void komeda_pipeline_dump_register(struct komeda_pipeline *pipe,
struct seq_file *sf)
{
struct komeda_component *c;
u32 id;
seq_printf(sf, "\n======== Pipeline-%d ==========\n", pipe->id);
if (pipe->funcs && pipe->funcs->dump_register)
pipe->funcs->dump_register(pipe, sf);
dp_for_each_set_bit(id, pipe->avail_comps) {
c = komeda_pipeline_get_component(pipe, id);
seq_printf(sf, "\n------%s------\n", c->name);
if (c->funcs->dump_register)
c->funcs->dump_register(c, sf);
}
}

54
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
View File

@ -204,29 +204,27 @@ static inline u16 component_changed_inputs(struct komeda_component_state *st)
return component_disabling_inputs(st) | st->changed_active_inputs;
}
#define for_each_changed_input(st, i) \
for ((i) = 0; (i) < (st)->component->max_active_inputs; (i)++) \
if (has_bit((i), component_changed_inputs(st)))
#define to_comp(__c) (((__c) == NULL) ? NULL : &((__c)->base))
#define to_cpos(__c) ((struct komeda_component **)&(__c))
/* these structures are going to be filled in in uture patches */
struct komeda_layer {
struct komeda_component base;
/* layer specific features and caps */
int layer_type; /* RICH, SIMPLE or WB */
/* accepted h/v input range before rotation */
struct malidp_range hsize_in, vsize_in;
u32 layer_type; /* RICH, SIMPLE or WB */
u32 supported_rots;
};
struct komeda_layer_state {
struct komeda_component_state base;
/* layer specific configuration state */
};
struct komeda_compiz {
struct komeda_component base;
/* compiz specific features and caps */
};
struct komeda_compiz_state {
struct komeda_component_state base;
/* compiz specific configuration state */
u16 hsize, vsize;
u32 rot;
dma_addr_t addr[3];
};
struct komeda_scaler {
@ -238,17 +236,42 @@ struct komeda_scaler_state {
struct komeda_component_state base;
};
struct komeda_compiz {
struct komeda_component base;
struct malidp_range hsize, vsize;
};
struct komeda_compiz_input_cfg {
u16 hsize, vsize;
u16 hoffset, voffset;
u8 pixel_blend_mode, layer_alpha;
};
struct komeda_compiz_state {
struct komeda_component_state base;
/* composition size */
u16 hsize, vsize;
struct komeda_compiz_input_cfg cins[KOMEDA_COMPONENT_N_INPUTS];
};
struct komeda_improc {
struct komeda_component base;
u32 supported_color_formats; /* DRM_RGB/YUV444/YUV420*/
u32 supported_color_depths; /* BIT(8) | BIT(10)*/
u8 supports_degamma : 1;
u8 supports_csc : 1;
u8 supports_gamma : 1;
};
struct komeda_improc_state {
struct komeda_component_state base;
u16 hsize, vsize;
};
/* display timing controller */
struct komeda_timing_ctrlr {
struct komeda_component base;
u8 supports_dual_link : 1;
};
struct komeda_timing_ctrlr_state {
@ -340,10 +363,13 @@ komeda_pipeline_add(struct komeda_dev *mdev, size_t size,
struct komeda_pipeline_funcs *funcs);
void komeda_pipeline_destroy(struct komeda_dev *mdev,
struct komeda_pipeline *pipe);
int komeda_assemble_pipelines(struct komeda_dev *mdev);
struct komeda_component *
komeda_pipeline_get_component(struct komeda_pipeline *pipe, int id);
void komeda_pipeline_dump_register(struct komeda_pipeline *pipe,
struct seq_file *sf);
/* component APIs */
struct komeda_component *
komeda_component_add(struct komeda_pipeline *pipe,