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net: dsa: qca8k: disable delay for RGMII mode 

In RGMII mode we should not have any delay in port MAC, so disable
the delay.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Vinod Koul 2019-01-21 14:43:18 +05:30 committed by David S. Miller
parent cd28d1d6e5
commit 5ecdd77c61
1 changed files with 4 additions and 12 deletions
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16
drivers/net/dsa/qca8k.c
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@ -420,7 +420,7 @@ qca8k_mib_init(struct qca8k_priv *priv)
static int static int
qca8k_set_pad_ctrl(struct qca8k_priv *priv, int port, int mode) qca8k_set_pad_ctrl(struct qca8k_priv *priv, int port, int mode)
{ {
u32 reg; u32 reg, val;
switch (port) { switch (port) {
case 0: case 0:
@ -439,17 +439,9 @@ qca8k_set_pad_ctrl(struct qca8k_priv *priv, int port, int mode)
*/ */
switch (mode) { switch (mode) {
case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII:
qca8k_write(priv, reg, /* RGMII mode means no delay so don't enable the delay */
QCA8K_PORT_PAD_RGMII_EN | val = QCA8K_PORT_PAD_RGMII_EN;
QCA8K_PORT_PAD_RGMII_TX_DELAY(3) | qca8k_write(priv, reg, val);
QCA8K_PORT_PAD_RGMII_RX_DELAY(3));
/* According to the datasheet, RGMII delay is enabled through
* PORT5_PAD_CTRL for all ports, rather than individual port
* registers
*/
qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
break; break;
case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_SGMII:
qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN); qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);