Allwinner DRM changes for 4.14
A few changes, but most notably improving the HDMI support merged in 4.13, by reporting the DDC adapter as an i2c bus, and by adding CEC support through the CEC framework. -----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJZl0SwAAoJEBx+YmzsjxAg4gkP/Rsyxww/f3+wX2COAc3uS0U9 +COEsvf0ztrVIP9xAIf+m29UxB9u6dP2KTKANFyAf4b42coW6fUimV4iQmdDKAxY Y/BNUV8SyDidFmxUo7Cy3uVFzA61+wsMPOXMpJA5uQa/eNpsbHEQhsZWEsYLymZF WV7h+Hepm+pVPTnbM1j5Pd2J+VISGBdacnXFjW2KzA+PdPoPT1fmKIQ39/OtPQzH RV1J4HPEVWZfZIJz9i2NK3J7GhRR5u9NnzfGZfWf0SHzujURuytJwgIvEm5dgLeD +XuUsCvVzkUB4jTY+T1qmVPQ+GcazyinKIu6ZU9pP1xkc+Apu79OapOdvmx95yIV l9l4Q0BuJvuWsZTP8lT4EMO7oyRE0oDleKgHQ6BbnqwTKY9pltEp4Wl7ovPibXje YjjierdO8WxUq8NhSW50S/EAu2oopbCp0YApdQVmMDlZ4bx41GWDmLlCaDsECakQ vQLtI5eQK1EbrQcJjioemdikt+xcrZ7+J35x1qLQ9aNwa49RI5WSIzOTxsqWHZYw 6wXv/HN6atPbRspnwgRlwtVYUOoSZ1xT+lST0rizRLJW4G8srzfPpjtXLaP8zWp+ IvJ+ntbn1O9CSBz70IovX/AnrWxMK3Guf1dFWE68JfSw/fxhUpF1RpHdi+yvZJpS xgedqXmmlYAMNlro9Ikg =6GJs -----END PGP SIGNATURE----- Merge tag 'sunxi-drm-for-4.14' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into drm-next Allwinner DRM changes for 4.14 A few changes, but most notably improving the HDMI support merged in 4.13, by reporting the DDC adapter as an i2c bus, and by adding CEC support through the CEC framework. * tag 'sunxi-drm-for-4.14' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: sun4i_hdmi: add CEC support dt-bindings: display: sunxi: Improve endpoint ID scheme readability drm/sun4i: tcon: remove unused function drm/sun4i: Remove useless atomic_check drm/sun4i: Add if statement instead of depends on drm/sun4i: hdmi: Implement I2C adapter for A10s DDC bus drm/sun4i: constify drm_plane_helper_funcs
This commit is contained in:
Dave Airlie
commit
5fd27c2a1f
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@ -4,15 +4,33 @@ Allwinner A10 Display Pipeline
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The Allwinner A10 Display pipeline is composed of several components
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that are going to be documented below:
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For the input port of all components up to the TCON in the display
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pipeline, if there are multiple components, the local endpoint IDs
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must correspond to the index of the upstream block. For example, if
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the remote endpoint is Frontend 1, then the local endpoint ID must
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be 1.
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For all connections between components up to the TCONs in the display
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pipeline, when there are multiple components of the same type at the
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same depth, the local endpoint ID must be the same as the remote
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component's index. For example, if the remote endpoint is Frontend 1,
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then the local endpoint ID must be 1.
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Conversely, for the output ports of the same group, the remote endpoint
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ID must be the index of the local hardware block. If the local backend
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is backend 1, then the remote endpoint ID must be 1.
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Frontend 0 [0] ------- [0] Backend 0 [0] ------- [0] TCON 0
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[1] -- -- [1] [1] -- -- [1]
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\ / \ /
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X X
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/ \ / \
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[0] -- -- [0] [0] -- -- [0]
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Frontend 1 [1] ------- [1] Backend 1 [1] ------- [1] TCON 1
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For a two pipeline system such as the one depicted above, the lines
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represent the connections between the components, while the numbers
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within the square brackets corresponds to the ID of the local endpoint.
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The same rule also applies to DE 2.0 mixer-TCON connections:
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Mixer 0 [0] ----------- [0] TCON 0
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[1] ---- ---- [1]
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\ /
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X
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/ \
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[0] ---- ---- [0]
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Mixer 1 [1] ----------- [1] TCON 1
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HDMI Encoder
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------------
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@ -13,17 +13,26 @@ config DRM_SUN4I
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Display Engine. If M is selected the module will be called
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sun4i-drm.
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if DRM_SUN4I
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config DRM_SUN4I_HDMI
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tristate "Allwinner A10 HDMI Controller Support"
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depends on DRM_SUN4I
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default DRM_SUN4I
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help
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Choose this option if you have an Allwinner SoC with an HDMI
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controller.
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config DRM_SUN4I_HDMI_CEC
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bool "Allwinner A10 HDMI CEC Support"
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depends on DRM_SUN4I_HDMI
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select CEC_CORE
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depends on CEC_PIN
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help
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Choose this option if you have an Allwinner SoC with an HDMI
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controller and want to use CEC.
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config DRM_SUN4I_BACKEND
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tristate "Support for Allwinner A10 Display Engine Backend"
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depends on DRM_SUN4I
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default DRM_SUN4I
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help
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Choose this option if you have an Allwinner SoC with the
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@ -33,10 +42,11 @@ config DRM_SUN4I_BACKEND
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config DRM_SUN8I_MIXER
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tristate "Support for Allwinner Display Engine 2.0 Mixer"
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depends on DRM_SUN4I
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default MACH_SUN8I
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help
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Choose this option if you have an Allwinner SoC with the
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Allwinner Display Engine 2.0, which has a mixer to do some
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graphics mixture and feed graphics to TCON, If M is
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selected the module will be called sun8i-mixer.
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endif
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@ -2,6 +2,7 @@ sun4i-drm-y += sun4i_drv.o
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sun4i-drm-y += sun4i_framebuffer.o
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sun4i-drm-hdmi-y += sun4i_hdmi_enc.o
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sun4i-drm-hdmi-y += sun4i_hdmi_i2c.o
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sun4i-drm-hdmi-y += sun4i_hdmi_ddc_clk.o
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sun4i-drm-hdmi-y += sun4i_hdmi_tmds_clk.o
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@ -15,6 +15,8 @@
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#include <drm/drm_connector.h>
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#include <drm/drm_encoder.h>
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#include <media/cec.h>
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#define SUN4I_HDMI_CTRL_REG 0x004
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#define SUN4I_HDMI_CTRL_ENABLE BIT(31)
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@ -86,6 +88,11 @@
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#define SUN4I_HDMI_PLL_DBG0_TMDS_PARENT_MASK BIT(21)
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#define SUN4I_HDMI_PLL_DBG0_TMDS_PARENT_SHIFT 21
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#define SUN4I_HDMI_CEC 0x214
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#define SUN4I_HDMI_CEC_ENABLE BIT(11)
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#define SUN4I_HDMI_CEC_TX BIT(9)
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#define SUN4I_HDMI_CEC_RX BIT(8)
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#define SUN4I_HDMI_PKT_CTRL_REG(n) (0x2f0 + (4 * (n)))
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#define SUN4I_HDMI_PKT_CTRL_TYPE(n, t) ((t) << (((n) % 4) * 4))
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@ -96,6 +103,7 @@
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#define SUN4I_HDMI_DDC_CTRL_ENABLE BIT(31)
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#define SUN4I_HDMI_DDC_CTRL_START_CMD BIT(30)
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#define SUN4I_HDMI_DDC_CTRL_FIFO_DIR_MASK BIT(8)
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#define SUN4I_HDMI_DDC_CTRL_FIFO_DIR_WRITE (1 << 8)
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#define SUN4I_HDMI_DDC_CTRL_FIFO_DIR_READ (0 << 8)
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#define SUN4I_HDMI_DDC_CTRL_RESET BIT(0)
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@ -105,14 +113,34 @@
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#define SUN4I_HDMI_DDC_ADDR_OFFSET(off) (((off) & 0xff) << 8)
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#define SUN4I_HDMI_DDC_ADDR_SLAVE(addr) ((addr) & 0xff)
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#define SUN4I_HDMI_DDC_INT_STATUS_REG 0x50c
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#define SUN4I_HDMI_DDC_INT_STATUS_ILLEGAL_FIFO_OPERATION BIT(7)
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#define SUN4I_HDMI_DDC_INT_STATUS_DDC_RX_FIFO_UNDERFLOW BIT(6)
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#define SUN4I_HDMI_DDC_INT_STATUS_DDC_TX_FIFO_OVERFLOW BIT(5)
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#define SUN4I_HDMI_DDC_INT_STATUS_FIFO_REQUEST BIT(4)
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#define SUN4I_HDMI_DDC_INT_STATUS_ARBITRATION_ERROR BIT(3)
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#define SUN4I_HDMI_DDC_INT_STATUS_ACK_ERROR BIT(2)
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#define SUN4I_HDMI_DDC_INT_STATUS_BUS_ERROR BIT(1)
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#define SUN4I_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE BIT(0)
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#define SUN4I_HDMI_DDC_FIFO_CTRL_REG 0x510
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#define SUN4I_HDMI_DDC_FIFO_CTRL_CLEAR BIT(31)
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#define SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES(n) (((n) & 0xf) << 4)
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#define SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES_MASK GENMASK(7, 4)
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#define SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES_MAX (BIT(4) - 1)
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#define SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES(n) ((n) & 0xf)
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#define SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES_MASK GENMASK(3, 0)
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#define SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES_MAX (BIT(4) - 1)
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#define SUN4I_HDMI_DDC_FIFO_DATA_REG 0x518
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#define SUN4I_HDMI_DDC_BYTE_COUNT_REG 0x51c
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#define SUN4I_HDMI_DDC_BYTE_COUNT_MAX (BIT(10) - 1)
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#define SUN4I_HDMI_DDC_CMD_REG 0x520
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#define SUN4I_HDMI_DDC_CMD_EXPLICIT_EDDC_READ 6
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#define SUN4I_HDMI_DDC_CMD_IMPLICIT_READ 5
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#define SUN4I_HDMI_DDC_CMD_IMPLICIT_WRITE 3
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#define SUN4I_HDMI_DDC_CLK_REG 0x528
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#define SUN4I_HDMI_DDC_CLK_M(m) (((m) & 0x7) << 3)
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@ -146,12 +174,16 @@ struct sun4i_hdmi {
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struct clk *ddc_clk;
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struct clk *tmds_clk;
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struct i2c_adapter *i2c;
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struct sun4i_drv *drv;
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bool hdmi_monitor;
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struct cec_adapter *cec_adap;
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};
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int sun4i_ddc_create(struct sun4i_hdmi *hdmi, struct clk *clk);
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int sun4i_tmds_create(struct sun4i_hdmi *hdmi);
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int sun4i_hdmi_i2c_create(struct device *dev, struct sun4i_hdmi *hdmi);
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#endif /* _SUN4I_HDMI_H_ */
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@ -29,8 +29,6 @@
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#include "sun4i_hdmi.h"
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#include "sun4i_tcon.h"
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#define DDC_SEGMENT_ADDR 0x30
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static inline struct sun4i_hdmi *
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drm_encoder_to_sun4i_hdmi(struct drm_encoder *encoder)
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{
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@ -184,93 +182,13 @@ static const struct drm_encoder_funcs sun4i_hdmi_funcs = {
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.destroy = drm_encoder_cleanup,
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};
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static int sun4i_hdmi_read_sub_block(struct sun4i_hdmi *hdmi,
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unsigned int blk, unsigned int offset,
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u8 *buf, unsigned int count)
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{
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unsigned long reg;
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int i;
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reg = readl(hdmi->base + SUN4I_HDMI_DDC_CTRL_REG);
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reg &= ~SUN4I_HDMI_DDC_CTRL_FIFO_DIR_MASK;
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writel(reg | SUN4I_HDMI_DDC_CTRL_FIFO_DIR_READ,
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hdmi->base + SUN4I_HDMI_DDC_CTRL_REG);
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writel(SUN4I_HDMI_DDC_ADDR_SEGMENT(offset >> 8) |
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SUN4I_HDMI_DDC_ADDR_EDDC(DDC_SEGMENT_ADDR << 1) |
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SUN4I_HDMI_DDC_ADDR_OFFSET(offset) |
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SUN4I_HDMI_DDC_ADDR_SLAVE(DDC_ADDR),
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hdmi->base + SUN4I_HDMI_DDC_ADDR_REG);
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reg = readl(hdmi->base + SUN4I_HDMI_DDC_FIFO_CTRL_REG);
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writel(reg | SUN4I_HDMI_DDC_FIFO_CTRL_CLEAR,
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hdmi->base + SUN4I_HDMI_DDC_FIFO_CTRL_REG);
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writel(count, hdmi->base + SUN4I_HDMI_DDC_BYTE_COUNT_REG);
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writel(SUN4I_HDMI_DDC_CMD_EXPLICIT_EDDC_READ,
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hdmi->base + SUN4I_HDMI_DDC_CMD_REG);
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reg = readl(hdmi->base + SUN4I_HDMI_DDC_CTRL_REG);
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writel(reg | SUN4I_HDMI_DDC_CTRL_START_CMD,
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hdmi->base + SUN4I_HDMI_DDC_CTRL_REG);
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if (readl_poll_timeout(hdmi->base + SUN4I_HDMI_DDC_CTRL_REG, reg,
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!(reg & SUN4I_HDMI_DDC_CTRL_START_CMD),
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100, 100000))
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return -EIO;
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for (i = 0; i < count; i++)
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buf[i] = readb(hdmi->base + SUN4I_HDMI_DDC_FIFO_DATA_REG);
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return 0;
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}
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static int sun4i_hdmi_read_edid_block(void *data, u8 *buf, unsigned int blk,
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size_t length)
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{
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struct sun4i_hdmi *hdmi = data;
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int retry = 2, i;
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do {
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for (i = 0; i < length; i += SUN4I_HDMI_DDC_FIFO_SIZE) {
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unsigned char offset = blk * EDID_LENGTH + i;
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unsigned int count = min((unsigned int)SUN4I_HDMI_DDC_FIFO_SIZE,
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length - i);
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int ret;
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ret = sun4i_hdmi_read_sub_block(hdmi, blk, offset,
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buf + i, count);
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if (ret)
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return ret;
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}
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} while (!drm_edid_block_valid(buf, blk, true, NULL) && (retry--));
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return 0;
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}
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static int sun4i_hdmi_get_modes(struct drm_connector *connector)
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{
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struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector);
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unsigned long reg;
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struct edid *edid;
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int ret;
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/* Reset i2c controller */
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writel(SUN4I_HDMI_DDC_CTRL_ENABLE | SUN4I_HDMI_DDC_CTRL_RESET,
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hdmi->base + SUN4I_HDMI_DDC_CTRL_REG);
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if (readl_poll_timeout(hdmi->base + SUN4I_HDMI_DDC_CTRL_REG, reg,
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!(reg & SUN4I_HDMI_DDC_CTRL_RESET),
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100, 2000))
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return -EIO;
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writel(SUN4I_HDMI_DDC_LINE_CTRL_SDA_ENABLE |
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SUN4I_HDMI_DDC_LINE_CTRL_SCL_ENABLE,
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hdmi->base + SUN4I_HDMI_DDC_LINE_CTRL_REG);
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clk_prepare_enable(hdmi->ddc_clk);
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clk_set_rate(hdmi->ddc_clk, 100000);
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edid = drm_do_get_edid(connector, sun4i_hdmi_read_edid_block, hdmi);
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edid = drm_get_edid(connector, hdmi->i2c);
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if (!edid)
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return 0;
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@ -279,11 +197,10 @@ static int sun4i_hdmi_get_modes(struct drm_connector *connector)
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hdmi->hdmi_monitor ? "an HDMI" : "a DVI");
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drm_mode_connector_update_edid_property(connector, edid);
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cec_s_phys_addr_from_edid(hdmi->cec_adap, edid);
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ret = drm_add_edid_modes(connector, edid);
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kfree(edid);
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clk_disable_unprepare(hdmi->ddc_clk);
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return ret;
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}
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@ -299,8 +216,10 @@ sun4i_hdmi_connector_detect(struct drm_connector *connector, bool force)
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if (readl_poll_timeout(hdmi->base + SUN4I_HDMI_HPD_REG, reg,
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reg & SUN4I_HDMI_HPD_HIGH,
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0, 500000))
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0, 500000)) {
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cec_phys_addr_invalidate(hdmi->cec_adap);
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return connector_status_disconnected;
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}
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return connector_status_connected;
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}
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@ -314,6 +233,40 @@ static const struct drm_connector_funcs sun4i_hdmi_connector_funcs = {
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.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
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};
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#ifdef CONFIG_DRM_SUN4I_HDMI_CEC
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static bool sun4i_hdmi_cec_pin_read(struct cec_adapter *adap)
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{
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struct sun4i_hdmi *hdmi = cec_get_drvdata(adap);
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|
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return readl(hdmi->base + SUN4I_HDMI_CEC) & SUN4I_HDMI_CEC_RX;
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}
|
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|
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static void sun4i_hdmi_cec_pin_low(struct cec_adapter *adap)
|
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{
|
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struct sun4i_hdmi *hdmi = cec_get_drvdata(adap);
|
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|
||||
/* Start driving the CEC pin low */
|
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writel(SUN4I_HDMI_CEC_ENABLE, hdmi->base + SUN4I_HDMI_CEC);
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}
|
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|
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static void sun4i_hdmi_cec_pin_high(struct cec_adapter *adap)
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{
|
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struct sun4i_hdmi *hdmi = cec_get_drvdata(adap);
|
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|
||||
/*
|
||||
* Stop driving the CEC pin, the pull up will take over
|
||||
* unless another CEC device is driving the pin low.
|
||||
*/
|
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writel(0, hdmi->base + SUN4I_HDMI_CEC);
|
||||
}
|
||||
|
||||
static const struct cec_pin_ops sun4i_hdmi_cec_pin_ops = {
|
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.read = sun4i_hdmi_cec_pin_read,
|
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.low = sun4i_hdmi_cec_pin_low,
|
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.high = sun4i_hdmi_cec_pin_high,
|
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};
|
||||
#endif
|
||||
|
||||
static int sun4i_hdmi_bind(struct device *dev, struct device *master,
|
||||
void *data)
|
||||
{
|
||||
|
|
@ -406,9 +359,9 @@ static int sun4i_hdmi_bind(struct device *dev, struct device *master,
|
|||
SUN4I_HDMI_PLL_CTRL_PLL_EN;
|
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writel(reg, hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
|
||||
|
||||
ret = sun4i_ddc_create(hdmi, hdmi->tmds_clk);
|
||||
ret = sun4i_hdmi_i2c_create(dev, hdmi);
|
||||
if (ret) {
|
||||
dev_err(dev, "Couldn't create the DDC clock\n");
|
||||
dev_err(dev, "Couldn't create the HDMI I2C adapter\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -421,13 +374,26 @@ static int sun4i_hdmi_bind(struct device *dev, struct device *master,
|
|||
NULL);
|
||||
if (ret) {
|
||||
dev_err(dev, "Couldn't initialise the HDMI encoder\n");
|
||||
return ret;
|
||||
goto err_del_i2c_adapter;
|
||||
}
|
||||
|
||||
hdmi->encoder.possible_crtcs = drm_of_find_possible_crtcs(drm,
|
||||
dev->of_node);
|
||||
if (!hdmi->encoder.possible_crtcs)
|
||||
return -EPROBE_DEFER;
|
||||
if (!hdmi->encoder.possible_crtcs) {
|
||||
ret = -EPROBE_DEFER;
|
||||
goto err_del_i2c_adapter;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DRM_SUN4I_HDMI_CEC
|
||||
hdmi->cec_adap = cec_pin_allocate_adapter(&sun4i_hdmi_cec_pin_ops,
|
||||
hdmi, "sun4i", CEC_CAP_TRANSMIT | CEC_CAP_LOG_ADDRS |
|
||||
CEC_CAP_PASSTHROUGH | CEC_CAP_RC);
|
||||
ret = PTR_ERR_OR_ZERO(hdmi->cec_adap);
|
||||
if (ret < 0)
|
||||
goto err_cleanup_connector;
|
||||
writel(readl(hdmi->base + SUN4I_HDMI_CEC) & ~SUN4I_HDMI_CEC_TX,
|
||||
hdmi->base + SUN4I_HDMI_CEC);
|
||||
#endif
|
||||
|
||||
drm_connector_helper_add(&hdmi->connector,
|
||||
&sun4i_hdmi_connector_helper_funcs);
|
||||
|
|
@ -444,12 +410,18 @@ static int sun4i_hdmi_bind(struct device *dev, struct device *master,
|
|||
hdmi->connector.polled = DRM_CONNECTOR_POLL_CONNECT |
|
||||
DRM_CONNECTOR_POLL_DISCONNECT;
|
||||
|
||||
ret = cec_register_adapter(hdmi->cec_adap, dev);
|
||||
if (ret < 0)
|
||||
goto err_cleanup_connector;
|
||||
drm_mode_connector_attach_encoder(&hdmi->connector, &hdmi->encoder);
|
||||
|
||||
return 0;
|
||||
|
||||
err_cleanup_connector:
|
||||
cec_delete_adapter(hdmi->cec_adap);
|
||||
drm_encoder_cleanup(&hdmi->encoder);
|
||||
err_del_i2c_adapter:
|
||||
i2c_del_adapter(hdmi->i2c);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -458,8 +430,10 @@ static void sun4i_hdmi_unbind(struct device *dev, struct device *master,
|
|||
{
|
||||
struct sun4i_hdmi *hdmi = dev_get_drvdata(dev);
|
||||
|
||||
cec_unregister_adapter(hdmi->cec_adap);
|
||||
drm_connector_cleanup(&hdmi->connector);
|
||||
drm_encoder_cleanup(&hdmi->encoder);
|
||||
i2c_del_adapter(hdmi->i2c);
|
||||
}
|
||||
|
||||
static const struct component_ops sun4i_hdmi_ops = {
|
||||
|
|
|
|||
|
|
@ -0,0 +1,220 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
|
||||
* Copyright (C) 2017 Jonathan Liu <net147@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/iopoll.h>
|
||||
|
||||
#include "sun4i_hdmi.h"
|
||||
|
||||
#define SUN4I_HDMI_DDC_INT_STATUS_ERROR_MASK ( \
|
||||
SUN4I_HDMI_DDC_INT_STATUS_ILLEGAL_FIFO_OPERATION | \
|
||||
SUN4I_HDMI_DDC_INT_STATUS_DDC_RX_FIFO_UNDERFLOW | \
|
||||
SUN4I_HDMI_DDC_INT_STATUS_DDC_TX_FIFO_OVERFLOW | \
|
||||
SUN4I_HDMI_DDC_INT_STATUS_ARBITRATION_ERROR | \
|
||||
SUN4I_HDMI_DDC_INT_STATUS_ACK_ERROR | \
|
||||
SUN4I_HDMI_DDC_INT_STATUS_BUS_ERROR \
|
||||
)
|
||||
|
||||
/* FIFO request bit is set when FIFO level is above RX_THRESHOLD during read */
|
||||
#define RX_THRESHOLD SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES_MAX
|
||||
/* FIFO request bit is set when FIFO level is below TX_THRESHOLD during write */
|
||||
#define TX_THRESHOLD 1
|
||||
|
||||
static int fifo_transfer(struct sun4i_hdmi *hdmi, u8 *buf, int len, bool read)
|
||||
{
|
||||
/*
|
||||
* 1 byte takes 9 clock cycles (8 bits + 1 ACK) = 90 us for 100 kHz
|
||||
* clock. As clock rate is fixed, just round it up to 100 us.
|
||||
*/
|
||||
const unsigned long byte_time_ns = 100;
|
||||
const u32 mask = SUN4I_HDMI_DDC_INT_STATUS_ERROR_MASK |
|
||||
SUN4I_HDMI_DDC_INT_STATUS_FIFO_REQUEST |
|
||||
SUN4I_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE;
|
||||
u32 reg;
|
||||
|
||||
/* Limit transfer length by FIFO threshold */
|
||||
len = min_t(int, len, read ? (RX_THRESHOLD + 1) :
|
||||
(SUN4I_HDMI_DDC_FIFO_SIZE - TX_THRESHOLD + 1));
|
||||
|
||||
/* Wait until error, FIFO request bit set or transfer complete */
|
||||
if (readl_poll_timeout(hdmi->base + SUN4I_HDMI_DDC_INT_STATUS_REG, reg,
|
||||
reg & mask, len * byte_time_ns, 100000))
|
||||
return -ETIMEDOUT;
|
||||
|
||||
if (reg & SUN4I_HDMI_DDC_INT_STATUS_ERROR_MASK)
|
||||
return -EIO;
|
||||
|
||||
if (read)
|
||||
readsb(hdmi->base + SUN4I_HDMI_DDC_FIFO_DATA_REG, buf, len);
|
||||
else
|
||||
writesb(hdmi->base + SUN4I_HDMI_DDC_FIFO_DATA_REG, buf, len);
|
||||
|
||||
/* Clear FIFO request bit */
|
||||
writel(SUN4I_HDMI_DDC_INT_STATUS_FIFO_REQUEST,
|
||||
hdmi->base + SUN4I_HDMI_DDC_INT_STATUS_REG);
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
static int xfer_msg(struct sun4i_hdmi *hdmi, struct i2c_msg *msg)
|
||||
{
|
||||
int i, len;
|
||||
u32 reg;
|
||||
|
||||
/* Set FIFO direction */
|
||||
reg = readl(hdmi->base + SUN4I_HDMI_DDC_CTRL_REG);
|
||||
reg &= ~SUN4I_HDMI_DDC_CTRL_FIFO_DIR_MASK;
|
||||
reg |= (msg->flags & I2C_M_RD) ?
|
||||
SUN4I_HDMI_DDC_CTRL_FIFO_DIR_READ :
|
||||
SUN4I_HDMI_DDC_CTRL_FIFO_DIR_WRITE;
|
||||
writel(reg, hdmi->base + SUN4I_HDMI_DDC_CTRL_REG);
|
||||
|
||||
/* Set I2C address */
|
||||
writel(SUN4I_HDMI_DDC_ADDR_SLAVE(msg->addr),
|
||||
hdmi->base + SUN4I_HDMI_DDC_ADDR_REG);
|
||||
|
||||
/* Set FIFO RX/TX thresholds and clear FIFO */
|
||||
reg = readl(hdmi->base + SUN4I_HDMI_DDC_FIFO_CTRL_REG);
|
||||
reg |= SUN4I_HDMI_DDC_FIFO_CTRL_CLEAR;
|
||||
reg &= ~SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES_MASK;
|
||||
reg |= SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES(RX_THRESHOLD);
|
||||
reg &= ~SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES_MASK;
|
||||
reg |= SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES(TX_THRESHOLD);
|
||||
writel(reg, hdmi->base + SUN4I_HDMI_DDC_FIFO_CTRL_REG);
|
||||
if (readl_poll_timeout(hdmi->base + SUN4I_HDMI_DDC_FIFO_CTRL_REG,
|
||||
reg,
|
||||
!(reg & SUN4I_HDMI_DDC_FIFO_CTRL_CLEAR),
|
||||
100, 2000))
|
||||
return -EIO;
|
||||
|
||||
/* Set transfer length */
|
||||
writel(msg->len, hdmi->base + SUN4I_HDMI_DDC_BYTE_COUNT_REG);
|
||||
|
||||
/* Set command */
|
||||
writel(msg->flags & I2C_M_RD ?
|
||||
SUN4I_HDMI_DDC_CMD_IMPLICIT_READ :
|
||||
SUN4I_HDMI_DDC_CMD_IMPLICIT_WRITE,
|
||||
hdmi->base + SUN4I_HDMI_DDC_CMD_REG);
|
||||
|
||||
/* Clear interrupt status bits */
|
||||
writel(SUN4I_HDMI_DDC_INT_STATUS_ERROR_MASK |
|
||||
SUN4I_HDMI_DDC_INT_STATUS_FIFO_REQUEST |
|
||||
SUN4I_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE,
|
||||
hdmi->base + SUN4I_HDMI_DDC_INT_STATUS_REG);
|
||||
|
||||
/* Start command */
|
||||
reg = readl(hdmi->base + SUN4I_HDMI_DDC_CTRL_REG);
|
||||
writel(reg | SUN4I_HDMI_DDC_CTRL_START_CMD,
|
||||
hdmi->base + SUN4I_HDMI_DDC_CTRL_REG);
|
||||
|
||||
/* Transfer bytes */
|
||||
for (i = 0; i < msg->len; i += len) {
|
||||
len = fifo_transfer(hdmi, msg->buf + i, msg->len - i,
|
||||
msg->flags & I2C_M_RD);
|
||||
if (len <= 0)
|
||||
return len;
|
||||
}
|
||||
|
||||
/* Wait for command to finish */
|
||||
if (readl_poll_timeout(hdmi->base + SUN4I_HDMI_DDC_CTRL_REG,
|
||||
reg,
|
||||
!(reg & SUN4I_HDMI_DDC_CTRL_START_CMD),
|
||||
100, 100000))
|
||||
return -EIO;
|
||||
|
||||
/* Check for errors */
|
||||
reg = readl(hdmi->base + SUN4I_HDMI_DDC_INT_STATUS_REG);
|
||||
if ((reg & SUN4I_HDMI_DDC_INT_STATUS_ERROR_MASK) ||
|
||||
!(reg & SUN4I_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE)) {
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sun4i_hdmi_i2c_xfer(struct i2c_adapter *adap,
|
||||
struct i2c_msg *msgs, int num)
|
||||
{
|
||||
struct sun4i_hdmi *hdmi = i2c_get_adapdata(adap);
|
||||
u32 reg;
|
||||
int err, i, ret = num;
|
||||
|
||||
for (i = 0; i < num; i++) {
|
||||
if (!msgs[i].len)
|
||||
return -EINVAL;
|
||||
if (msgs[i].len > SUN4I_HDMI_DDC_BYTE_COUNT_MAX)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Reset I2C controller */
|
||||
writel(SUN4I_HDMI_DDC_CTRL_ENABLE | SUN4I_HDMI_DDC_CTRL_RESET,
|
||||
hdmi->base + SUN4I_HDMI_DDC_CTRL_REG);
|
||||
if (readl_poll_timeout(hdmi->base + SUN4I_HDMI_DDC_CTRL_REG, reg,
|
||||
!(reg & SUN4I_HDMI_DDC_CTRL_RESET),
|
||||
100, 2000))
|
||||
return -EIO;
|
||||
|
||||
writel(SUN4I_HDMI_DDC_LINE_CTRL_SDA_ENABLE |
|
||||
SUN4I_HDMI_DDC_LINE_CTRL_SCL_ENABLE,
|
||||
hdmi->base + SUN4I_HDMI_DDC_LINE_CTRL_REG);
|
||||
|
||||
clk_prepare_enable(hdmi->ddc_clk);
|
||||
clk_set_rate(hdmi->ddc_clk, 100000);
|
||||
|
||||
for (i = 0; i < num; i++) {
|
||||
err = xfer_msg(hdmi, &msgs[i]);
|
||||
if (err) {
|
||||
ret = err;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
clk_disable_unprepare(hdmi->ddc_clk);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static u32 sun4i_hdmi_i2c_func(struct i2c_adapter *adap)
|
||||
{
|
||||
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
|
||||
}
|
||||
|
||||
static const struct i2c_algorithm sun4i_hdmi_i2c_algorithm = {
|
||||
.master_xfer = sun4i_hdmi_i2c_xfer,
|
||||
.functionality = sun4i_hdmi_i2c_func,
|
||||
};
|
||||
|
||||
int sun4i_hdmi_i2c_create(struct device *dev, struct sun4i_hdmi *hdmi)
|
||||
{
|
||||
struct i2c_adapter *adap;
|
||||
int ret = 0;
|
||||
|
||||
ret = sun4i_ddc_create(hdmi, hdmi->tmds_clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
adap = devm_kzalloc(dev, sizeof(*adap), GFP_KERNEL);
|
||||
if (!adap)
|
||||
return -ENOMEM;
|
||||
|
||||
adap->owner = THIS_MODULE;
|
||||
adap->class = I2C_CLASS_DDC;
|
||||
adap->algo = &sun4i_hdmi_i2c_algorithm;
|
||||
strlcpy(adap->name, "sun4i_hdmi_i2c adapter", sizeof(adap->name));
|
||||
i2c_set_adapdata(adap, hdmi);
|
||||
|
||||
ret = i2c_add_adapter(adap);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
hdmi->i2c = adap;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -25,12 +25,6 @@ struct sun4i_plane_desc {
|
|||
uint32_t nformats;
|
||||
};
|
||||
|
||||
static int sun4i_backend_layer_atomic_check(struct drm_plane *plane,
|
||||
struct drm_plane_state *state)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void sun4i_backend_layer_atomic_disable(struct drm_plane *plane,
|
||||
struct drm_plane_state *old_state)
|
||||
{
|
||||
|
|
@ -52,8 +46,7 @@ static void sun4i_backend_layer_atomic_update(struct drm_plane *plane,
|
|||
sun4i_backend_layer_enable(backend, layer->id, true);
|
||||
}
|
||||
|
||||
static struct drm_plane_helper_funcs sun4i_backend_layer_helper_funcs = {
|
||||
.atomic_check = sun4i_backend_layer_atomic_check,
|
||||
static const struct drm_plane_helper_funcs sun4i_backend_layer_helper_funcs = {
|
||||
.atomic_disable = sun4i_backend_layer_atomic_disable,
|
||||
.atomic_update = sun4i_backend_layer_atomic_update,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -127,13 +127,6 @@ static const struct drm_connector_funcs sun4i_rgb_con_funcs = {
|
|||
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
|
||||
};
|
||||
|
||||
static int sun4i_rgb_atomic_check(struct drm_encoder *encoder,
|
||||
struct drm_crtc_state *crtc_state,
|
||||
struct drm_connector_state *conn_state)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void sun4i_rgb_encoder_enable(struct drm_encoder *encoder)
|
||||
{
|
||||
struct sun4i_rgb *rgb = drm_encoder_to_sun4i_rgb(encoder);
|
||||
|
|
@ -181,7 +174,6 @@ static void sun4i_rgb_encoder_mode_set(struct drm_encoder *encoder,
|
|||
}
|
||||
|
||||
static struct drm_encoder_helper_funcs sun4i_rgb_enc_helper_funcs = {
|
||||
.atomic_check = sun4i_rgb_atomic_check,
|
||||
.mode_set = sun4i_rgb_encoder_mode_set,
|
||||
.disable = sun4i_rgb_encoder_disable,
|
||||
.enable = sun4i_rgb_encoder_enable,
|
||||
|
|
|
|||
|
|
@ -194,8 +194,6 @@ void sun4i_tcon_channel_enable(struct sun4i_tcon *tcon, int channel);
|
|||
void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable);
|
||||
|
||||
/* Mode Related Controls */
|
||||
void sun4i_tcon_switch_interlace(struct sun4i_tcon *tcon,
|
||||
bool enable);
|
||||
void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel,
|
||||
struct drm_encoder *encoder);
|
||||
void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon,
|
||||
|
|
|
|||
|
|
@ -341,13 +341,6 @@ static void sun4i_tv_mode_to_drm_mode(const struct tv_mode *tv_mode,
|
|||
mode->vtotal = mode->vsync_end + tv_mode->vback_porch;
|
||||
}
|
||||
|
||||
static int sun4i_tv_atomic_check(struct drm_encoder *encoder,
|
||||
struct drm_crtc_state *crtc_state,
|
||||
struct drm_connector_state *conn_state)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void sun4i_tv_disable(struct drm_encoder *encoder)
|
||||
{
|
||||
struct sun4i_tv *tv = drm_encoder_to_sun4i_tv(encoder);
|
||||
|
|
@ -489,7 +482,6 @@ static void sun4i_tv_mode_set(struct drm_encoder *encoder,
|
|||
}
|
||||
|
||||
static struct drm_encoder_helper_funcs sun4i_tv_helper_funcs = {
|
||||
.atomic_check = sun4i_tv_atomic_check,
|
||||
.disable = sun4i_tv_disable,
|
||||
.enable = sun4i_tv_enable,
|
||||
.mode_set = sun4i_tv_mode_set,
|
||||
|
|
|
|||
Loading…
Reference in New Issue