PCI: dwc: dra7xx: Add EP mode support
The PCIe controller integrated in dra7xx SoCs is capable of operating in endpoint mode. Add endpoint mode support to dra7xx driver. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
This commit is contained in:
Kishon Vijay Abraham I
Bjorn Helgaas
parent
5ffd90a035
commit
608793e27b
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@ -16,14 +16,37 @@ config PCIE_DW_EP
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config PCI_DRA7XX
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bool "TI DRA7xx PCIe controller"
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depends on PCI
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depends on (PCI && PCI_MSI_IRQ_DOMAIN) || PCI_ENDPOINT
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depends on OF && HAS_IOMEM && TI_PIPE3
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help
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Enables support for the PCIe controller in the DRA7xx SoC. There
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are two instances of PCIe controller in DRA7xx. This controller can
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work either as EP or RC. In order to enable host-specific features
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PCI_DRA7XX_HOST must be selected and in order to enable device-
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specific features PCI_DRA7XX_EP must be selected. This uses
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the Designware core.
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if PCI_DRA7XX
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config PCI_DRA7XX_HOST
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bool "PCI DRA7xx Host Mode"
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depends on PCI
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depends on PCI_MSI_IRQ_DOMAIN
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select PCIE_DW_HOST
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default y
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help
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Enables support for the PCIe controller in the DRA7xx SoC. There
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are two instances of PCIe controller in DRA7xx. This controller can
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act both as EP and RC. This reuses the Designware core.
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Enables support for the PCIe controller in the DRA7xx SoC to work in
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host mode.
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config PCI_DRA7XX_EP
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bool "PCI DRA7xx Endpoint Mode"
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depends on PCI_ENDPOINT
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select PCIE_DW_EP
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help
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Enables support for the PCIe controller in the DRA7xx SoC to work in
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endpoint mode.
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endif
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config PCIE_DW_PLAT
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bool "Platform bus based DesignWare PCIe Controller"
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@ -2,7 +2,9 @@ obj-$(CONFIG_PCIE_DW) += pcie-designware.o
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obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
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obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
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obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
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obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
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ifneq ($(filter y,$(CONFIG_PCI_DRA7XX_HOST) $(CONFIG_PCI_DRA7XX_EP)),)
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obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
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endif
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obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
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obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
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obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
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@ -10,12 +10,14 @@
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* published by the Free Software Foundation.
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*/
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/of_device.h>
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#include <linux/of_gpio.h>
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#include <linux/of_pci.h>
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#include <linux/pci.h>
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@ -57,6 +59,11 @@
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#define MSI BIT(4)
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#define LEG_EP_INTERRUPTS (INTA | INTB | INTC | INTD)
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#define PCIECTRL_TI_CONF_DEVICE_TYPE 0x0100
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#define DEVICE_TYPE_EP 0x0
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#define DEVICE_TYPE_LEG_EP 0x1
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#define DEVICE_TYPE_RC 0x4
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#define PCIECTRL_DRA7XX_CONF_DEVICE_CMD 0x0104
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#define LTSSM_EN 0x1
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@ -66,6 +73,13 @@
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#define EXP_CAP_ID_OFFSET 0x70
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#define PCIECTRL_TI_CONF_INTX_ASSERT 0x0124
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#define PCIECTRL_TI_CONF_INTX_DEASSERT 0x0128
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#define PCIECTRL_TI_CONF_MSI_XMT 0x012c
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#define MSI_REQ_GRANT BIT(0)
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#define MSI_VECTOR_SHIFT 7
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struct dra7xx_pcie {
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struct dw_pcie *pci;
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void __iomem *base; /* DT ti_conf */
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@ -73,6 +87,11 @@ struct dra7xx_pcie {
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struct phy **phy;
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int link_gen;
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struct irq_domain *irq_domain;
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enum dw_pcie_device_mode mode;
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};
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struct dra7xx_pcie_of_data {
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enum dw_pcie_device_mode mode;
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};
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#define to_dra7xx_pcie(x) dev_get_drvdata((x)->dev)
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@ -101,9 +120,19 @@ static int dra7xx_pcie_link_up(struct dw_pcie *pci)
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return !!(reg & LINK_UP);
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}
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static int dra7xx_pcie_establish_link(struct dra7xx_pcie *dra7xx)
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static void dra7xx_pcie_stop_link(struct dw_pcie *pci)
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{
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struct dw_pcie *pci = dra7xx->pci;
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struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
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u32 reg;
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reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
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reg &= ~LTSSM_EN;
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dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
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}
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static int dra7xx_pcie_establish_link(struct dw_pcie *pci)
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{
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struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
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struct device *dev = pci->dev;
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u32 reg;
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u32 exp_cap_off = EXP_CAP_ID_OFFSET;
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@ -137,7 +166,7 @@ static int dra7xx_pcie_establish_link(struct dra7xx_pcie *dra7xx)
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reg |= LTSSM_EN;
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dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
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return dw_pcie_wait_for_link(pci);
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return 0;
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}
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static void dra7xx_pcie_enable_msi_interrupts(struct dra7xx_pcie *dra7xx)
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@ -171,7 +200,8 @@ static void dra7xx_pcie_host_init(struct pcie_port *pp)
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dw_pcie_setup_rc(pp);
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dra7xx_pcie_establish_link(dra7xx);
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dra7xx_pcie_establish_link(pci);
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dw_pcie_wait_for_link(pci);
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dw_pcie_msi_init(pp);
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dra7xx_pcie_enable_interrupts(dra7xx);
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}
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@ -249,6 +279,7 @@ static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
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struct dra7xx_pcie *dra7xx = arg;
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struct dw_pcie *pci = dra7xx->pci;
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struct device *dev = pci->dev;
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struct dw_pcie_ep *ep = &pci->ep;
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u32 reg;
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reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN);
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@ -285,8 +316,11 @@ static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
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if (reg & LINK_REQ_RST)
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dev_dbg(dev, "Link Request Reset\n");
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if (reg & LINK_UP_EVT)
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if (reg & LINK_UP_EVT) {
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if (dra7xx->mode == DW_PCIE_EP_TYPE)
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dw_pcie_ep_linkup(ep);
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dev_dbg(dev, "Link-up state change\n");
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}
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if (reg & CFG_BME_EVT)
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dev_dbg(dev, "CFG 'Bus Master Enable' change\n");
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@ -299,6 +333,94 @@ static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
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return IRQ_HANDLED;
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}
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static void dra7xx_pcie_ep_init(struct dw_pcie_ep *ep)
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{
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
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dra7xx_pcie_enable_wrapper_interrupts(dra7xx);
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}
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static void dra7xx_pcie_raise_legacy_irq(struct dra7xx_pcie *dra7xx)
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{
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dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_INTX_ASSERT, 0x1);
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mdelay(1);
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dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_INTX_DEASSERT, 0x1);
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}
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static void dra7xx_pcie_raise_msi_irq(struct dra7xx_pcie *dra7xx,
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u8 interrupt_num)
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{
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u32 reg;
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reg = (interrupt_num - 1) << MSI_VECTOR_SHIFT;
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reg |= MSI_REQ_GRANT;
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dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_MSI_XMT, reg);
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}
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static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep,
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enum pci_epc_irq_type type, u8 interrupt_num)
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{
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
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switch (type) {
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case PCI_EPC_IRQ_LEGACY:
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dra7xx_pcie_raise_legacy_irq(dra7xx);
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break;
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case PCI_EPC_IRQ_MSI:
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dra7xx_pcie_raise_msi_irq(dra7xx, interrupt_num);
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break;
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default:
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dev_err(pci->dev, "UNKNOWN IRQ type\n");
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}
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return 0;
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}
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static struct dw_pcie_ep_ops pcie_ep_ops = {
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.ep_init = dra7xx_pcie_ep_init,
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.raise_irq = dra7xx_pcie_raise_irq,
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};
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static int __init dra7xx_add_pcie_ep(struct dra7xx_pcie *dra7xx,
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struct platform_device *pdev)
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{
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int ret;
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struct dw_pcie_ep *ep;
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struct resource *res;
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struct device *dev = &pdev->dev;
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struct dw_pcie *pci = dra7xx->pci;
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ep = &pci->ep;
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ep->ops = &pcie_ep_ops;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ep_dbics");
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pci->dbi_base = devm_ioremap(dev, res->start, resource_size(res));
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if (!pci->dbi_base)
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return -ENOMEM;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ep_dbics2");
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pci->dbi_base2 = devm_ioremap(dev, res->start, resource_size(res));
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if (!pci->dbi_base2)
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return -ENOMEM;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
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if (!res)
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return -EINVAL;
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ep->phys_base = res->start;
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ep->addr_size = resource_size(res);
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ret = dw_pcie_ep_init(ep);
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if (ret) {
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dev_err(dev, "failed to initialize endpoint\n");
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return ret;
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}
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return 0;
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}
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static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
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struct platform_device *pdev)
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{
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@ -342,6 +464,8 @@ static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
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static const struct dw_pcie_ops dw_pcie_ops = {
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.cpu_addr_fixup = dra7xx_pcie_cpu_addr_fixup,
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.start_link = dra7xx_pcie_establish_link,
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.stop_link = dra7xx_pcie_stop_link,
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.link_up = dra7xx_pcie_link_up,
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};
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@ -384,6 +508,26 @@ static int dra7xx_pcie_enable_phy(struct dra7xx_pcie *dra7xx)
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return ret;
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}
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static const struct dra7xx_pcie_of_data dra7xx_pcie_rc_of_data = {
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.mode = DW_PCIE_RC_TYPE,
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};
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static const struct dra7xx_pcie_of_data dra7xx_pcie_ep_of_data = {
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.mode = DW_PCIE_EP_TYPE,
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};
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static const struct of_device_id of_dra7xx_pcie_match[] = {
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{
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.compatible = "ti,dra7-pcie",
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.data = &dra7xx_pcie_rc_of_data,
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},
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{
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.compatible = "ti,dra7-pcie-ep",
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.data = &dra7xx_pcie_ep_of_data,
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},
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{},
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};
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static int __init dra7xx_pcie_probe(struct platform_device *pdev)
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{
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u32 reg;
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@ -401,6 +545,16 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
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struct device_node *np = dev->of_node;
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char name[10];
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struct gpio_desc *reset;
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const struct of_device_id *match;
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const struct dra7xx_pcie_of_data *data;
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enum dw_pcie_device_mode mode;
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match = of_match_device(of_match_ptr(of_dra7xx_pcie_match), dev);
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if (!match)
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return -EINVAL;
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data = (struct dra7xx_pcie_of_data *)match->data;
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mode = (enum dw_pcie_device_mode)data->mode;
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dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL);
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if (!dra7xx)
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@ -479,9 +633,25 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
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if (dra7xx->link_gen < 0 || dra7xx->link_gen > 2)
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dra7xx->link_gen = 2;
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ret = dra7xx_add_pcie_port(dra7xx, pdev);
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if (ret < 0)
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goto err_gpio;
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switch (mode) {
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case DW_PCIE_RC_TYPE:
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dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
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DEVICE_TYPE_RC);
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ret = dra7xx_add_pcie_port(dra7xx, pdev);
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if (ret < 0)
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goto err_gpio;
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break;
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case DW_PCIE_EP_TYPE:
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dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
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DEVICE_TYPE_EP);
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ret = dra7xx_add_pcie_ep(dra7xx, pdev);
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if (ret < 0)
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goto err_gpio;
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break;
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default:
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dev_err(dev, "INVALID device type %d\n", mode);
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}
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dra7xx->mode = mode;
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ret = devm_request_irq(dev, irq, dra7xx_pcie_irq_handler,
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IRQF_SHARED, "dra7xx-pcie-main", dra7xx);
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@ -509,6 +679,9 @@ static int dra7xx_pcie_suspend(struct device *dev)
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struct dw_pcie *pci = dra7xx->pci;
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u32 val;
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if (dra7xx->mode != DW_PCIE_RC_TYPE)
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return 0;
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/* clear MSE */
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val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
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val &= ~PCI_COMMAND_MEMORY;
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@ -523,6 +696,9 @@ static int dra7xx_pcie_resume(struct device *dev)
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struct dw_pcie *pci = dra7xx->pci;
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u32 val;
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if (dra7xx->mode != DW_PCIE_RC_TYPE)
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return 0;
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/* set MSE */
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val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
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val |= PCI_COMMAND_MEMORY;
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@ -561,11 +737,6 @@ static const struct dev_pm_ops dra7xx_pcie_pm_ops = {
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dra7xx_pcie_resume_noirq)
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};
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static const struct of_device_id of_dra7xx_pcie_match[] = {
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{ .compatible = "ti,dra7-pcie", },
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{},
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};
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static struct platform_driver dra7xx_pcie_driver = {
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.driver = {
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.name = "dra7-pcie",
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@ -120,6 +120,13 @@ enum dw_pcie_region_type {
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DW_PCIE_REGION_OUTBOUND,
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};
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enum dw_pcie_device_mode {
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DW_PCIE_UNKNOWN_TYPE,
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DW_PCIE_EP_TYPE,
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DW_PCIE_LEG_EP_TYPE,
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DW_PCIE_RC_TYPE,
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};
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struct dw_pcie_host_ops {
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int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val);
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int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val);
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