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drm/amd/display: drop dc_validate_guaranteed 

Block FP16 scaling in validate_resources codepath.

Signed-off-by: Julian Parkin <jparkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Julian Parkin 2018-03-13 15:53:13 -04:00 committed by Alex Deucher
parent f8931ea730
commit 6133470c8e
12 changed files with 7 additions and 234 deletions
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32
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
View File

@ -1599,18 +1599,6 @@ enum dc_status dc_remove_stream_from_ctx(
return DC_OK;
}
static void copy_pipe_ctx(
const struct pipe_ctx *from_pipe_ctx, struct pipe_ctx *to_pipe_ctx)
{
struct dc_plane_state *plane_state = to_pipe_ctx->plane_state;
struct dc_stream_state *stream = to_pipe_ctx->stream;
*to_pipe_ctx = *from_pipe_ctx;
to_pipe_ctx->stream = stream;
if (plane_state != NULL)
to_pipe_ctx->plane_state = plane_state;
}
static struct dc_stream_state *find_pll_sharable_stream(
struct dc_stream_state *stream_needs_pll,
struct dc_state *context)
@ -1752,26 +1740,6 @@ enum dc_status resource_map_pool_resources(
return DC_ERROR_UNEXPECTED;
}
/* first stream in the context is used to populate the rest */
void validate_guaranteed_copy_streams(
struct dc_state *context,
int max_streams)
{
int i;
for (i = 1; i < max_streams; i++) {
context->streams[i] = context->streams[0];
copy_pipe_ctx(&context->res_ctx.pipe_ctx[0],
&context->res_ctx.pipe_ctx[i]);
context->res_ctx.pipe_ctx[i].stream =
context->res_ctx.pipe_ctx[0].stream;
dc_stream_retain(context->streams[i]);
context->stream_count++;
}
}
void dc_resource_state_copy_construct_current(
const struct dc *dc,
struct dc_state *dst_ctx)

8
drivers/gpu/drm/amd/display/dc/dc_stream.h
View File

@ -208,14 +208,6 @@ bool dc_add_all_planes_for_stream(
enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream);
/*
* This function takes a stream and checks if it is guaranteed to be supported.
* Guaranteed means that MAX_COFUNC similar streams are supported.
*
* After this call:
* No hardware is programmed for call. Only validation is done.
*/
/*
* Set up streams and links associated to drive sinks
* The streams parameter is an absolute set of all active streams.

33
drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
View File

@ -733,38 +733,6 @@ enum dc_status dce100_add_stream_to_ctx(
return result;
}
enum dc_status dce100_validate_guaranteed(
struct dc *dc,
struct dc_stream_state *dc_stream,
struct dc_state *context)
{
enum dc_status result = DC_ERROR_UNEXPECTED;
context->streams[0] = dc_stream;
dc_stream_retain(context->streams[0]);
context->stream_count++;
result = resource_map_pool_resources(dc, context, dc_stream);
if (result == DC_OK)
result = resource_map_clock_resources(dc, context, dc_stream);
if (result == DC_OK)
result = build_mapped_resource(dc, context, dc_stream);
if (result == DC_OK) {
validate_guaranteed_copy_streams(
context, dc->caps.max_streams);
result = resource_build_scaling_params_for_context(dc, context);
}
if (result == DC_OK)
if (!dce100_validate_bandwidth(dc, context))
result = DC_FAIL_BANDWIDTH_VALIDATE;
return result;
}
static void dce100_destroy_resource_pool(struct resource_pool **pool)
{
struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
@ -786,7 +754,6 @@ enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, s
static const struct resource_funcs dce100_res_pool_funcs = {
.destroy = dce100_destroy_resource_pool,
.link_enc_create = dce100_link_encoder_create,
.validate_guaranteed = dce100_validate_guaranteed,
.validate_bandwidth = dce100_validate_bandwidth,
.validate_plane = dce100_validate_plane,
.add_stream_to_ctx = dce100_add_stream_to_ctx,

33
drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
View File

@ -930,38 +930,6 @@ static enum dc_status dce110_add_stream_to_ctx(
return result;
}
static enum dc_status dce110_validate_guaranteed(
struct dc *dc,
struct dc_stream_state *dc_stream,
struct dc_state *context)
{
enum dc_status result = DC_ERROR_UNEXPECTED;
context->streams[0] = dc_stream;
dc_stream_retain(context->streams[0]);
context->stream_count++;
result = resource_map_pool_resources(dc, context, dc_stream);
if (result == DC_OK)
result = resource_map_clock_resources(dc, context, dc_stream);
if (result == DC_OK)
result = build_mapped_resource(dc, context, dc_stream);
if (result == DC_OK) {
validate_guaranteed_copy_streams(
context, dc->caps.max_streams);
result = resource_build_scaling_params_for_context(dc, context);
}
if (result == DC_OK)
if (!dce110_validate_bandwidth(dc, context))
result = DC_FAIL_BANDWIDTH_VALIDATE;
return result;
}
static struct pipe_ctx *dce110_acquire_underlay(
struct dc_state *context,
const struct resource_pool *pool,
@ -1036,7 +1004,6 @@ static void dce110_destroy_resource_pool(struct resource_pool **pool)
static const struct resource_funcs dce110_res_pool_funcs = {
.destroy = dce110_destroy_resource_pool,
.link_enc_create = dce110_link_encoder_create,
.validate_guaranteed = dce110_validate_guaranteed,
.validate_bandwidth = dce110_validate_bandwidth,
.validate_plane = dce110_validate_plane,
.acquire_idle_pipe_for_layer = dce110_acquire_underlay,

33
drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
View File

@ -867,38 +867,6 @@ enum dc_status dce112_add_stream_to_ctx(
return result;
}
enum dc_status dce112_validate_guaranteed(
struct dc *dc,
struct dc_stream_state *stream,
struct dc_state *context)
{
enum dc_status result = DC_ERROR_UNEXPECTED;
context->streams[0] = stream;
dc_stream_retain(context->streams[0]);
context->stream_count++;
result = resource_map_pool_resources(dc, context, stream);
if (result == DC_OK)
result = resource_map_phy_clock_resources(dc, context, stream);
if (result == DC_OK)
result = build_mapped_resource(dc, context, stream);
if (result == DC_OK) {
validate_guaranteed_copy_streams(
context, dc->caps.max_streams);
result = resource_build_scaling_params_for_context(dc, context);
}
if (result == DC_OK)
if (!dce112_validate_bandwidth(dc, context))
result = DC_FAIL_BANDWIDTH_VALIDATE;
return result;
}
enum dc_status dce112_validate_global(
struct dc *dc,
struct dc_state *context)
@ -921,7 +889,6 @@ static void dce112_destroy_resource_pool(struct resource_pool **pool)
static const struct resource_funcs dce112_res_pool_funcs = {
.destroy = dce112_destroy_resource_pool,
.link_enc_create = dce112_link_encoder_create,
.validate_guaranteed = dce112_validate_guaranteed,
.validate_bandwidth = dce112_validate_bandwidth,
.validate_plane = dce100_validate_plane,
.add_stream_to_ctx = dce112_add_stream_to_ctx,

5
drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h
View File

@ -42,11 +42,6 @@ enum dc_status dce112_validate_with_context(
struct dc_state *context,
struct dc_state *old_context);
enum dc_status dce112_validate_guaranteed(
struct dc *dc,
struct dc_stream_state *dc_stream,
struct dc_state *context);
bool dce112_validate_bandwidth(
struct dc *dc,
struct dc_state *context);

1
drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
View File

@ -684,7 +684,6 @@ static void dce120_destroy_resource_pool(struct resource_pool **pool)
static const struct resource_funcs dce120_res_pool_funcs = {
.destroy = dce120_destroy_resource_pool,
.link_enc_create = dce120_link_encoder_create,
.validate_guaranteed = dce112_validate_guaranteed,
.validate_bandwidth = dce112_validate_bandwidth,
.validate_plane = dce100_validate_plane,
.add_stream_to_ctx = dce112_add_stream_to_ctx

49
drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
View File

@ -691,23 +691,6 @@ static void destruct(struct dce110_resource_pool *pool)
}
}
static enum dc_status build_mapped_resource(
const struct dc *dc,
struct dc_state *context,
struct dc_stream_state *stream)
{
struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
if (!pipe_ctx)
return DC_ERROR_UNEXPECTED;
dce110_resource_build_pipe_hw_param(pipe_ctx);
resource_build_info_frame(pipe_ctx);
return DC_OK;
}
bool dce80_validate_bandwidth(
struct dc *dc,
struct dc_state *context)
@ -749,37 +732,6 @@ enum dc_status dce80_validate_global(
return DC_OK;
}
enum dc_status dce80_validate_guaranteed(
struct dc *dc,
struct dc_stream_state *dc_stream,
struct dc_state *context)
{
enum dc_status result = DC_ERROR_UNEXPECTED;
context->streams[0] = dc_stream;
dc_stream_retain(context->streams[0]);
context->stream_count++;
result = resource_map_pool_resources(dc, context, dc_stream);
if (result == DC_OK)
result = resource_map_clock_resources(dc, context, dc_stream);
if (result == DC_OK)
result = build_mapped_resource(dc, context, dc_stream);
if (result == DC_OK) {
validate_guaranteed_copy_streams(
context, dc->caps.max_streams);
result = resource_build_scaling_params_for_context(dc, context);
}
if (result == DC_OK)
result = dce80_validate_bandwidth(dc, context);
return result;
}
static void dce80_destroy_resource_pool(struct resource_pool **pool)
{
struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
@ -792,7 +744,6 @@ static void dce80_destroy_resource_pool(struct resource_pool **pool)
static const struct resource_funcs dce80_res_pool_funcs = {
.destroy = dce80_destroy_resource_pool,
.link_enc_create = dce80_link_encoder_create,
.validate_guaranteed = dce80_validate_guaranteed,
.validate_bandwidth = dce80_validate_bandwidth,
.validate_plane = dce100_validate_plane,
.add_stream_to_ctx = dce100_add_stream_to_ctx,

7
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
View File

@ -121,6 +121,13 @@ bool dpp_get_optimal_number_of_taps(
else
pixel_width = scl_data->viewport.width;
/* Some ASICs does not support FP16 scaling, so we reject modes require this*/
if (scl_data->viewport.width != scl_data->h_active &&
scl_data->viewport.height != scl_data->v_active &&
dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT &&
scl_data->format == PIXEL_FORMAT_FP16)
return false;
/* TODO: add lb check */
/* No support for programming ratio of 4, drop to 3.99999.. */

31
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
View File

@ -918,36 +918,6 @@ enum dc_status dcn10_add_stream_to_ctx(
return result;
}
enum dc_status dcn10_validate_guaranteed(
struct dc *dc,
struct dc_stream_state *dc_stream,
struct dc_state *context)
{
enum dc_status result = DC_ERROR_UNEXPECTED;
context->streams[0] = dc_stream;
dc_stream_retain(context->streams[0]);
context->stream_count++;
result = resource_map_pool_resources(dc, context, dc_stream);
if (result == DC_OK)
result = resource_map_phy_clock_resources(dc, context, dc_stream);
if (result == DC_OK)
result = build_mapped_resource(dc, context, dc_stream);
if (result == DC_OK) {
validate_guaranteed_copy_streams(
context, dc->caps.max_streams);
result = resource_build_scaling_params_for_context(dc, context);
}
if (result == DC_OK && !dcn_validate_bandwidth(dc, context))
return DC_FAIL_BANDWIDTH_VALIDATE;
return result;
}
static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer(
struct dc_state *context,
const struct resource_pool *pool,
@ -1233,7 +1203,6 @@ static struct dc_cap_funcs cap_funcs = {
static struct resource_funcs dcn10_res_pool_funcs = {
.destroy = dcn10_destroy_resource_pool,
.link_enc_create = dcn10_link_encoder_create,
.validate_guaranteed = dcn10_validate_guaranteed,
.validate_bandwidth = dcn_validate_bandwidth,
.acquire_idle_pipe_for_layer = dcn10_acquire_idle_pipe_for_layer,
.validate_plane = dcn10_validate_plane,

5
drivers/gpu/drm/amd/display/dc/inc/core_types.h
View File

@ -95,11 +95,6 @@ struct resource_funcs {
struct link_encoder *(*link_enc_create)(
const struct encoder_init_data *init);
enum dc_status (*validate_guaranteed)(
struct dc *dc,
struct dc_stream_state *stream,
struct dc_state *context);
bool (*validate_bandwidth)(
struct dc *dc,
struct dc_state *context);

4
drivers/gpu/drm/amd/display/dc/inc/resource.h
View File

@ -139,10 +139,6 @@ bool resource_validate_attach_surfaces(
struct dc_state *context,
const struct resource_pool *pool);
void validate_guaranteed_copy_streams(
struct dc_state *context,
int max_streams);
void resource_validate_ctx_update_pointer_after_copy(
const struct dc_state *src_ctx,
struct dc_state *dst_ctx);