Drivers: hv: vmbus: Remove x86 MSR refs in arch independent code
In architecture independent code for manipulating Hyper-V synthetic timers and synthetic interrupts, pass in an ordinal number identifying the timer or interrupt, rather than an actual MSR register address. Then in x86/x64 specific code, map the ordinal number to the appropriate MSR. This change facilitates the introduction of an ARM64 version of Hyper-V, which uses the same synthetic timers and interrupts, but a different mechanism for accessing them. Signed-off-by: Michael Kelley <mikelley@microsoft.com> Signed-off-by: K. Y. Srinivasan <kys@microsoft.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -75,8 +75,10 @@ static inline void vmbus_signal_eom(struct hv_message *msg, u32 old_msg_type)
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}
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}
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#define hv_init_timer(timer, tick) wrmsrl(timer, tick)
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#define hv_init_timer_config(config, val) wrmsrl(config, val)
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#define hv_init_timer(timer, tick) \
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wrmsrl(HV_X64_MSR_STIMER0_COUNT + (2*timer), tick)
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#define hv_init_timer_config(timer, val) \
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wrmsrl(HV_X64_MSR_STIMER0_CONFIG + (2*timer), val)
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#define hv_get_simp(val) rdmsrl(HV_X64_MSR_SIMP, val)
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#define hv_set_simp(val) wrmsrl(HV_X64_MSR_SIMP, val)
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@ -89,8 +91,10 @@ static inline void vmbus_signal_eom(struct hv_message *msg, u32 old_msg_type)
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#define hv_get_vp_index(index) rdmsrl(HV_X64_MSR_VP_INDEX, index)
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#define hv_get_synint_state(int_num, val) rdmsrl(int_num, val)
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#define hv_set_synint_state(int_num, val) wrmsrl(int_num, val)
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#define hv_get_synint_state(int_num, val) \
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rdmsrl(HV_X64_MSR_SINT0 + int_num, val)
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#define hv_set_synint_state(int_num, val) \
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wrmsrl(HV_X64_MSR_SINT0 + int_num, val)
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void hyperv_callback_vector(void);
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void hyperv_reenlightenment_vector(void);
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@ -127,14 +127,14 @@ static int hv_ce_set_next_event(unsigned long delta,
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current_tick = hyperv_cs->read(NULL);
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current_tick += delta;
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hv_init_timer(HV_X64_MSR_STIMER0_COUNT, current_tick);
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hv_init_timer(0, current_tick);
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return 0;
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}
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static int hv_ce_shutdown(struct clock_event_device *evt)
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{
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hv_init_timer(HV_X64_MSR_STIMER0_COUNT, 0);
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hv_init_timer_config(HV_X64_MSR_STIMER0_CONFIG, 0);
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hv_init_timer(0, 0);
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hv_init_timer_config(0, 0);
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if (direct_mode_enabled)
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hv_disable_stimer0_percpu_irq(stimer0_irq);
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@ -164,7 +164,7 @@ static int hv_ce_set_oneshot(struct clock_event_device *evt)
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timer_cfg.direct_mode = 0;
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timer_cfg.sintx = VMBUS_MESSAGE_SINT;
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}
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hv_init_timer_config(HV_X64_MSR_STIMER0_CONFIG, timer_cfg.as_uint64);
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hv_init_timer_config(0, timer_cfg.as_uint64);
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return 0;
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}
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@ -298,8 +298,7 @@ int hv_synic_init(unsigned int cpu)
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hv_set_siefp(siefp.as_uint64);
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/* Setup the shared SINT. */
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hv_get_synint_state(HV_X64_MSR_SINT0 + VMBUS_MESSAGE_SINT,
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shared_sint.as_uint64);
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hv_get_synint_state(VMBUS_MESSAGE_SINT, shared_sint.as_uint64);
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shared_sint.vector = HYPERVISOR_CALLBACK_VECTOR;
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shared_sint.masked = false;
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@ -308,8 +307,7 @@ int hv_synic_init(unsigned int cpu)
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else
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shared_sint.auto_eoi = true;
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hv_set_synint_state(HV_X64_MSR_SINT0 + VMBUS_MESSAGE_SINT,
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shared_sint.as_uint64);
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hv_set_synint_state(VMBUS_MESSAGE_SINT, shared_sint.as_uint64);
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/* Enable the global synic bit */
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hv_get_synic_state(sctrl.as_uint64);
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@ -405,15 +403,13 @@ int hv_synic_cleanup(unsigned int cpu)
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put_cpu_ptr(hv_cpu);
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}
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hv_get_synint_state(HV_X64_MSR_SINT0 + VMBUS_MESSAGE_SINT,
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shared_sint.as_uint64);
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hv_get_synint_state(VMBUS_MESSAGE_SINT, shared_sint.as_uint64);
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shared_sint.masked = 1;
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/* Need to correctly cleanup in the case of SMP!!! */
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/* Disable the interrupt */
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hv_set_synint_state(HV_X64_MSR_SINT0 + VMBUS_MESSAGE_SINT,
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shared_sint.as_uint64);
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hv_set_synint_state(VMBUS_MESSAGE_SINT, shared_sint.as_uint64);
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hv_get_simp(simp.as_uint64);
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simp.simp_enabled = 0;
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