ARM: integrator: Convert PCI to use generic config accessors
Convert the integrator PCI driver to use the generic config access functions. This changes accesses from __raw_readX/__raw_writeX to readX/writeX variants. The spinlock is removed because it is unnecessary. The config read and write functions are already protected with a spinlock and no access can occur during the .pre_init function. [arnd: remove unused "flags"] Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> CC: Russell King <linux@arm.linux.org.uk> CC: linux-arm-kernel@lists.infradead.org
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@ -356,7 +356,6 @@ static u64 pre_mem_pci_sz;
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* 7:2 register number
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* 7:2 register number
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*
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*
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*/
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*/
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static DEFINE_RAW_SPINLOCK(v3_lock);
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#undef V3_LB_BASE_PREFETCH
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#undef V3_LB_BASE_PREFETCH
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#define V3_LB_BASE_PREFETCH 0
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#define V3_LB_BASE_PREFETCH 0
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@ -457,67 +456,21 @@ static void v3_close_config_window(void)
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static int v3_read_config(struct pci_bus *bus, unsigned int devfn, int where,
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static int v3_read_config(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 *val)
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int size, u32 *val)
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{
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{
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void __iomem *addr;
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int ret = pci_generic_config_read(bus, devfn, where, size, val);
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unsigned long flags;
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u32 v;
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raw_spin_lock_irqsave(&v3_lock, flags);
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addr = v3_open_config_window(bus, devfn, where);
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switch (size) {
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case 1:
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v = __raw_readb(addr);
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break;
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case 2:
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v = __raw_readw(addr);
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break;
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default:
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v = __raw_readl(addr);
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break;
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}
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v3_close_config_window();
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v3_close_config_window();
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raw_spin_unlock_irqrestore(&v3_lock, flags);
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return ret;
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*val = v;
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return PCIBIOS_SUCCESSFUL;
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}
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}
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static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where,
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static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 val)
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int size, u32 val)
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{
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{
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void __iomem *addr;
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int ret = pci_generic_config_write(bus, devfn, where, size, val);
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unsigned long flags;
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raw_spin_lock_irqsave(&v3_lock, flags);
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addr = v3_open_config_window(bus, devfn, where);
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switch (size) {
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case 1:
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__raw_writeb((u8)val, addr);
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__raw_readb(addr);
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break;
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case 2:
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__raw_writew((u16)val, addr);
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__raw_readw(addr);
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break;
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case 4:
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__raw_writel(val, addr);
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__raw_readl(addr);
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break;
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}
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v3_close_config_window();
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v3_close_config_window();
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raw_spin_unlock_irqrestore(&v3_lock, flags);
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return ret;
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return PCIBIOS_SUCCESSFUL;
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}
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}
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static struct pci_ops pci_v3_ops = {
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static struct pci_ops pci_v3_ops = {
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.map_bus = v3_open_config_window,
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.read = v3_read_config,
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.read = v3_read_config,
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.write = v3_write_config,
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.write = v3_write_config,
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};
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};
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@ -658,7 +611,6 @@ static int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
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*/
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*/
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static void __init pci_v3_preinit(void)
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static void __init pci_v3_preinit(void)
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{
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{
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unsigned long flags;
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unsigned int temp;
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unsigned int temp;
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phys_addr_t io_address = pci_pio_to_address(io_mem.start);
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phys_addr_t io_address = pci_pio_to_address(io_mem.start);
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@ -672,8 +624,6 @@ static void __init pci_v3_preinit(void)
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hook_fault_code(8, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch");
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hook_fault_code(8, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch");
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hook_fault_code(10, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch");
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hook_fault_code(10, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch");
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raw_spin_lock_irqsave(&v3_lock, flags);
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/*
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/*
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* Unlock V3 registers, but only if they were previously locked.
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* Unlock V3 registers, but only if they were previously locked.
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*/
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*/
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@ -736,8 +686,6 @@ static void __init pci_v3_preinit(void)
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v3_writew(V3_LB_CFG, v3_readw(V3_LB_CFG) | (1 << 10));
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v3_writew(V3_LB_CFG, v3_readw(V3_LB_CFG) | (1 << 10));
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v3_writeb(V3_LB_IMASK, 0x28);
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v3_writeb(V3_LB_IMASK, 0x28);
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__raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET);
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__raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET);
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raw_spin_unlock_irqrestore(&v3_lock, flags);
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}
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}
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static void __init pci_v3_postinit(void)
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static void __init pci_v3_postinit(void)
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