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drm: mali-dp: Rename malidp_input_format to malidp_pixel_format 

We're going to use the same format list for output formats, so rename
everything related to input formats to avoid confusion.

Signed-off-by: Brian Starkey <brian.starkey@arm.com>
[touched commit title to clarify the final struct name]
Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
This commit is contained in:
Brian Starkey 2016-10-03 15:08:12 +01:00 committed by Liviu Dudau
parent c7ffa59cf0
commit 6211b4868e
3 changed files with 20 additions and 20 deletions
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24
drivers/gpu/drm/arm/malidp_hw.c
View File

@ -21,7 +21,7 @@
#include "malidp_drv.h" #include "malidp_drv.h"
#include "malidp_hw.h" #include "malidp_hw.h"
static const struct malidp_input_format malidp500_de_formats[] = { static const struct malidp_format_id malidp500_de_formats[] = {
/* fourcc, layers supporting the format, internal id */ /* fourcc, layers supporting the format, internal id */
{ DRM_FORMAT_ARGB2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 0 }, { DRM_FORMAT_ARGB2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 0 },
{ DRM_FORMAT_ABGR2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 1 }, { DRM_FORMAT_ABGR2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 1 },
@ -69,7 +69,7 @@ static const struct malidp_input_format malidp500_de_formats[] = {
{ DRM_FORMAT_NV12, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 6) }, \ { DRM_FORMAT_NV12, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 6) }, \
{ DRM_FORMAT_YUV420, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 7) } { DRM_FORMAT_YUV420, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 7) }
static const struct malidp_input_format malidp550_de_formats[] = { static const struct malidp_format_id malidp550_de_formats[] = {
MALIDP_COMMON_FORMATS, MALIDP_COMMON_FORMATS,
}; };
@ -436,8 +436,8 @@ const struct malidp_hw_device malidp_device[MALIDP_MAX_DEVICES] = {
.irq_mask = MALIDP500_DE_IRQ_CONF_VALID, .irq_mask = MALIDP500_DE_IRQ_CONF_VALID,
.vsync_irq = MALIDP500_DE_IRQ_CONF_VALID, .vsync_irq = MALIDP500_DE_IRQ_CONF_VALID,
}, },
.input_formats = malidp500_de_formats, .pixel_formats = malidp500_de_formats,
.n_input_formats = ARRAY_SIZE(malidp500_de_formats), .n_pixel_formats = ARRAY_SIZE(malidp500_de_formats),
.bus_align_bytes = 8, .bus_align_bytes = 8,
}, },
.query_hw = malidp500_query_hw, .query_hw = malidp500_query_hw,
@ -469,8 +469,8 @@ const struct malidp_hw_device malidp_device[MALIDP_MAX_DEVICES] = {
.irq_mask = MALIDP550_DC_IRQ_CONF_VALID, .irq_mask = MALIDP550_DC_IRQ_CONF_VALID,
.vsync_irq = MALIDP550_DC_IRQ_CONF_VALID, .vsync_irq = MALIDP550_DC_IRQ_CONF_VALID,
}, },
.input_formats = malidp550_de_formats, .pixel_formats = malidp550_de_formats,
.n_input_formats = ARRAY_SIZE(malidp550_de_formats), .n_pixel_formats = ARRAY_SIZE(malidp550_de_formats),
.bus_align_bytes = 8, .bus_align_bytes = 8,
}, },
.query_hw = malidp550_query_hw, .query_hw = malidp550_query_hw,
@ -503,8 +503,8 @@ const struct malidp_hw_device malidp_device[MALIDP_MAX_DEVICES] = {
.irq_mask = MALIDP550_DC_IRQ_CONF_VALID, .irq_mask = MALIDP550_DC_IRQ_CONF_VALID,
.vsync_irq = MALIDP550_DC_IRQ_CONF_VALID, .vsync_irq = MALIDP550_DC_IRQ_CONF_VALID,
}, },
.input_formats = malidp550_de_formats, .pixel_formats = malidp550_de_formats,
.n_input_formats = ARRAY_SIZE(malidp550_de_formats), .n_pixel_formats = ARRAY_SIZE(malidp550_de_formats),
.bus_align_bytes = 16, .bus_align_bytes = 16,
}, },
.query_hw = malidp650_query_hw, .query_hw = malidp650_query_hw,
@ -522,10 +522,10 @@ u8 malidp_hw_get_format_id(const struct malidp_hw_regmap *map,
{ {
unsigned int i; unsigned int i;
for (i = 0; i < map->n_input_formats; i++) { for (i = 0; i < map->n_pixel_formats; i++) {
if (((map->input_formats[i].layer & layer_id) == layer_id) && if (((map->pixel_formats[i].layer & layer_id) == layer_id) &&
(map->input_formats[i].format == format)) (map->pixel_formats[i].format == format))
return map->input_formats[i].id; return map->pixel_formats[i].id;
} }
return MALIDP_INVALID_FORMAT_ID; return MALIDP_INVALID_FORMAT_ID;

8
drivers/gpu/drm/arm/malidp_hw.h
View File

@ -35,7 +35,7 @@ enum {
DE_SMART = BIT(4), DE_SMART = BIT(4),
}; };
struct malidp_input_format { struct malidp_format_id {
u32 format; /* DRM fourcc */ u32 format; /* DRM fourcc */
u8 layer; /* bitmask of layers supporting it */ u8 layer; /* bitmask of layers supporting it */
u8 id; /* used internally */ u8 id; /* used internally */
@ -85,9 +85,9 @@ struct malidp_hw_regmap {
const struct malidp_irq_map se_irq_map; const struct malidp_irq_map se_irq_map;
const struct malidp_irq_map dc_irq_map; const struct malidp_irq_map dc_irq_map;
/* list of supported input formats for each layer */ /* list of supported pixel formats for each layer */
const struct malidp_input_format *input_formats; const struct malidp_format_id *pixel_formats;
const u8 n_input_formats; const u8 n_pixel_formats;
/* pitch alignment requirement in bytes */ /* pitch alignment requirement in bytes */
const u8 bus_align_bytes; const u8 bus_align_bytes;

8
drivers/gpu/drm/arm/malidp_planes.c
View File

@ -267,7 +267,7 @@ int malidp_de_planes_init(struct drm_device *drm)
u32 *formats; u32 *formats;
int ret, i, j, n; int ret, i, j, n;
formats = kcalloc(map->n_input_formats, sizeof(*formats), GFP_KERNEL); formats = kcalloc(map->n_pixel_formats, sizeof(*formats), GFP_KERNEL);
if (!formats) { if (!formats) {
ret = -ENOMEM; ret = -ENOMEM;
goto cleanup; goto cleanup;
@ -283,9 +283,9 @@ int malidp_de_planes_init(struct drm_device *drm)
} }
/* build the list of DRM supported formats based on the map */ /* build the list of DRM supported formats based on the map */
for (n = 0, j = 0; j < map->n_input_formats; j++) { for (n = 0, j = 0; j < map->n_pixel_formats; j++) {
if ((map->input_formats[j].layer & id) == id) if ((map->pixel_formats[j].layer & id) == id)
formats[n++] = map->input_formats[j].format; formats[n++] = map->pixel_formats[j].format;
} }
plane_type = (i == 0) ? DRM_PLANE_TYPE_PRIMARY : plane_type = (i == 0) ? DRM_PLANE_TYPE_PRIMARY :