net/mlx5e: XDP, Add user control for XDP TX MPWQE feature
Add ethtool private flag 'xdp_tx_mpwqe' to control the feature from userspace. Feature is set ON by default, if supported. Signed-off-by: Tariq Toukan <tariqt@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
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@ -216,6 +216,7 @@ enum mlx5e_priv_flag {
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MLX5E_PFLAG_RX_CQE_COMPRESS,
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MLX5E_PFLAG_RX_CQE_COMPRESS,
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MLX5E_PFLAG_RX_STRIDING_RQ,
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MLX5E_PFLAG_RX_STRIDING_RQ,
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MLX5E_PFLAG_RX_NO_CSUM_COMPLETE,
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MLX5E_PFLAG_RX_NO_CSUM_COMPLETE,
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MLX5E_PFLAG_XDP_TX_MPWQE,
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MLX5E_NUM_PFLAGS, /* Keep last */
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MLX5E_NUM_PFLAGS, /* Keep last */
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};
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};
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@ -1672,12 +1672,40 @@ static int set_pflag_rx_no_csum_complete(struct net_device *netdev, bool enable)
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return 0;
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return 0;
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}
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}
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static int set_pflag_xdp_tx_mpwqe(struct net_device *netdev, bool enable)
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{
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struct mlx5e_priv *priv = netdev_priv(netdev);
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struct mlx5_core_dev *mdev = priv->mdev;
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struct mlx5e_channels new_channels = {};
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int err;
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if (enable && !MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
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return -EOPNOTSUPP;
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new_channels.params = priv->channels.params;
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MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_XDP_TX_MPWQE, enable);
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if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
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priv->channels.params = new_channels.params;
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return 0;
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}
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err = mlx5e_open_channels(priv, &new_channels);
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if (err)
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return err;
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mlx5e_switch_priv_channels(priv, &new_channels, NULL);
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return 0;
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}
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static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS] = {
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static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS] = {
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{ "rx_cqe_moder", set_pflag_rx_cqe_based_moder },
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{ "rx_cqe_moder", set_pflag_rx_cqe_based_moder },
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{ "tx_cqe_moder", set_pflag_tx_cqe_based_moder },
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{ "tx_cqe_moder", set_pflag_tx_cqe_based_moder },
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{ "rx_cqe_compress", set_pflag_rx_cqe_compress },
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{ "rx_cqe_compress", set_pflag_rx_cqe_compress },
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{ "rx_striding_rq", set_pflag_rx_striding_rq },
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{ "rx_striding_rq", set_pflag_rx_striding_rq },
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{ "rx_no_csum_complete", set_pflag_rx_no_csum_complete },
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{ "rx_no_csum_complete", set_pflag_rx_no_csum_complete },
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{ "xdp_tx_mpwqe", set_pflag_xdp_tx_mpwqe },
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};
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};
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static int mlx5e_handle_pflag(struct net_device *netdev,
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static int mlx5e_handle_pflag(struct net_device *netdev,
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@ -2341,7 +2341,7 @@ static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
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mlx5e_build_sq_param_common(priv, param);
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mlx5e_build_sq_param_common(priv, param);
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MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
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MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
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param->is_mpw = MLX5_CAP_ETH(priv->mdev, enhanced_multi_pkt_send_wqe);
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param->is_mpw = MLX5E_GET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE);
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}
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}
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static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
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static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
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@ -4595,6 +4595,10 @@ void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
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MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
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MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
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MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
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MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
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/* XDP SQ */
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MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE,
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MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe));
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/* set CQE compression */
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/* set CQE compression */
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params->rx_cqe_compress_def = false;
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params->rx_cqe_compress_def = false;
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if (MLX5_CAP_GEN(mdev, cqe_compression) &&
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if (MLX5_CAP_GEN(mdev, cqe_compression) &&
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