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ARM: dts: r8a7792: add VIN clocks 

Describe the VIN[0-5] clocks and their parent, ZG clock in the R8A7792
device  tree.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Sergei Shtylyov 2016-07-23 22:16:38 +03:00 committed by Simon Horman
parent 78082700c8
commit 62855bcf15
1 changed files with 17 additions and 3 deletions
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20
arch/arm/boot/dts/r8a7792.dtsi
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@ -643,6 +643,13 @@ rcan_clk: rcan {
clock-div = <49>; clock-div = <49>;
clock-mult = <1>; clock-mult = <1>;
}; };
zg_clk: zg {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <5>;
clock-mult = <1>;
};
/* Gate clocks */ /* Gate clocks */
mstp1_clks: mstp1_clks@e6150134 { mstp1_clks: mstp1_clks@e6150134 {
@ -702,10 +709,17 @@ mstp8_clks: mstp8_clks@e6150990 {
compatible = "renesas,r8a7792-mstp-clocks", compatible = "renesas,r8a7792-mstp-clocks",
"renesas,cpg-mstp-clocks"; "renesas,cpg-mstp-clocks";
reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
clocks = <&hp_clk>; clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
<&zg_clk>, <&zg_clk>, <&hp_clk>;
#clock-cells = <1>; #clock-cells = <1>;
clock-indices = <R8A7792_CLK_ETHERAVB>; clock-indices = <
clock-output-names = "etheravb"; R8A7792_CLK_VIN5 R8A7792_CLK_VIN4
R8A7792_CLK_VIN3 R8A7792_CLK_VIN2
R8A7792_CLK_VIN1 R8A7792_CLK_VIN0
R8A7792_CLK_ETHERAVB
>;
clock-output-names = "vin5", "vin4", "vin3", "vin2",
"vin1", "vin0", "etheravb";
}; };
mstp9_clks: mstp9_clks@e6150994 { mstp9_clks: mstp9_clks@e6150994 {
compatible = "renesas,r8a7792-mstp-clocks", compatible = "renesas,r8a7792-mstp-clocks",