ath9k: Add initvals for QCA956x

Signed-off-by: Miaoqing Pan <miaoqing@qca.qualcomm.com>
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
This commit is contained in:
Miaoqing Pan 2014-12-19 06:33:57 +05:30 committed by Kalle Valo
parent 2131fabb4b
commit 635d7c50a0
2 changed files with 1106 additions and 1 deletions

View File

@ -29,6 +29,7 @@
#include "ar9565_1p0_initvals.h" #include "ar9565_1p0_initvals.h"
#include "ar9565_1p1_initvals.h" #include "ar9565_1p1_initvals.h"
#include "ar953x_initvals.h" #include "ar953x_initvals.h"
#include "ar956x_initvals.h"
/* General hardware code for the AR9003 hadware family */ /* General hardware code for the AR9003 hadware family */
@ -358,6 +359,40 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
INIT_INI_ARRAY(&ah->iniModesFastClock, INIT_INI_ARRAY(&ah->iniModesFastClock,
qca953x_1p0_modes_fast_clock); qca953x_1p0_modes_fast_clock);
} else if (AR_SREV_9561(ah)) {
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
qca956x_1p0_mac_core);
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
qca956x_1p0_mac_postamble);
INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
qca956x_1p0_baseband_core);
INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
qca956x_1p0_baseband_postamble);
INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
qca956x_1p0_radio_core);
INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
qca956x_1p0_radio_postamble);
INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
qca956x_1p0_soc_preamble);
INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
qca956x_1p0_soc_postamble);
INIT_INI_ARRAY(&ah->iniModesRxGain,
qca956x_1p0_common_wo_xlna_rx_gain_table);
INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
qca956x_1p0_common_wo_xlna_rx_gain_bounds);
INIT_INI_ARRAY(&ah->iniModesTxGain,
qca956x_1p0_modes_no_xpa_tx_gain_table);
INIT_INI_ARRAY(&ah->ini_dfs,
qca956x_1p0_baseband_postamble_dfs_channel);
INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
qca956x_1p0_baseband_core_txfir_coeff_japan_2484);
INIT_INI_ARRAY(&ah->iniModesFastClock,
qca956x_1p0_modes_fast_clock);
} else if (AR_SREV_9580(ah)) { } else if (AR_SREV_9580(ah)) {
/* mac */ /* mac */
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
@ -544,6 +579,9 @@ static void ar9003_tx_gain_table_mode0(struct ath_hw *ah)
else if (AR_SREV_9531_20(ah)) else if (AR_SREV_9531_20(ah))
INIT_INI_ARRAY(&ah->iniModesTxGain, INIT_INI_ARRAY(&ah->iniModesTxGain,
qca953x_2p0_modes_xpa_tx_gain_table); qca953x_2p0_modes_xpa_tx_gain_table);
else if (AR_SREV_9561(ah))
INIT_INI_ARRAY(&ah->iniModesTxGain,
qca956x_1p0_modes_xpa_tx_gain_table);
else if (AR_SREV_9580(ah)) else if (AR_SREV_9580(ah))
INIT_INI_ARRAY(&ah->iniModesTxGain, INIT_INI_ARRAY(&ah->iniModesTxGain,
ar9580_1p0_lowest_ob_db_tx_gain_table); ar9580_1p0_lowest_ob_db_tx_gain_table);
@ -594,7 +632,10 @@ static void ar9003_tx_gain_table_mode1(struct ath_hw *ah)
else else
INIT_INI_ARRAY(&ah->iniModesTxGain, INIT_INI_ARRAY(&ah->iniModesTxGain,
qca953x_1p0_modes_no_xpa_tx_gain_table); qca953x_1p0_modes_no_xpa_tx_gain_table);
} else if (AR_SREV_9462_21(ah)) } else if (AR_SREV_9561(ah))
INIT_INI_ARRAY(&ah->iniModesTxGain,
qca956x_1p0_modes_no_xpa_tx_gain_table);
else if (AR_SREV_9462_21(ah))
INIT_INI_ARRAY(&ah->iniModesTxGain, INIT_INI_ARRAY(&ah->iniModesTxGain,
ar9462_2p1_modes_high_ob_db_tx_gain); ar9462_2p1_modes_high_ob_db_tx_gain);
else if (AR_SREV_9462_20(ah)) else if (AR_SREV_9462_20(ah))
@ -628,6 +669,9 @@ static void ar9003_tx_gain_table_mode2(struct ath_hw *ah)
else if (AR_SREV_9580(ah)) else if (AR_SREV_9580(ah))
INIT_INI_ARRAY(&ah->iniModesTxGain, INIT_INI_ARRAY(&ah->iniModesTxGain,
ar9580_1p0_low_ob_db_tx_gain_table); ar9580_1p0_low_ob_db_tx_gain_table);
else if (AR_SREV_9561(ah))
INIT_INI_ARRAY(&ah->iniModesTxGain,
qca956x_1p0_modes_no_xpa_low_ob_db_tx_gain_table);
else if (AR_SREV_9565_11(ah)) else if (AR_SREV_9565_11(ah))
INIT_INI_ARRAY(&ah->iniModesTxGain, INIT_INI_ARRAY(&ah->iniModesTxGain,
ar9565_1p1_modes_low_ob_db_tx_gain_table); ar9565_1p1_modes_low_ob_db_tx_gain_table);
@ -699,6 +743,9 @@ static void ar9003_tx_gain_table_mode5(struct ath_hw *ah)
else if (AR_SREV_9580(ah)) else if (AR_SREV_9580(ah))
INIT_INI_ARRAY(&ah->iniModesTxGain, INIT_INI_ARRAY(&ah->iniModesTxGain,
ar9580_1p0_type5_tx_gain_table); ar9580_1p0_type5_tx_gain_table);
else if (AR_SREV_9561(ah))
INIT_INI_ARRAY(&ah->iniModesTxGain,
qca956x_1p0_modes_no_xpa_green_tx_gain_table);
else if (AR_SREV_9300_22(ah)) else if (AR_SREV_9300_22(ah))
INIT_INI_ARRAY(&ah->iniModesTxGain, INIT_INI_ARRAY(&ah->iniModesTxGain,
ar9300Modes_type5_tx_gain_table_2p2); ar9300Modes_type5_tx_gain_table_2p2);
@ -770,6 +817,13 @@ static void ar9003_rx_gain_table_mode0(struct ath_hw *ah)
qca953x_1p0_common_rx_gain_table); qca953x_1p0_common_rx_gain_table);
INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds, INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
qca953x_1p0_common_rx_gain_bounds); qca953x_1p0_common_rx_gain_bounds);
} else if (AR_SREV_9561(ah)) {
INIT_INI_ARRAY(&ah->iniModesRxGain,
qca956x_1p0_common_rx_gain_table);
INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
qca956x_1p0_common_rx_gain_bounds);
INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
qca956x_1p0_xlna_only);
} else if (AR_SREV_9580(ah)) } else if (AR_SREV_9580(ah))
INIT_INI_ARRAY(&ah->iniModesRxGain, INIT_INI_ARRAY(&ah->iniModesRxGain,
ar9580_1p0_rx_gain_table); ar9580_1p0_rx_gain_table);
@ -825,6 +879,11 @@ static void ar9003_rx_gain_table_mode1(struct ath_hw *ah)
qca953x_2p0_common_wo_xlna_rx_gain_table); qca953x_2p0_common_wo_xlna_rx_gain_table);
INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds, INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
qca953x_2p0_common_wo_xlna_rx_gain_bounds); qca953x_2p0_common_wo_xlna_rx_gain_bounds);
} else if (AR_SREV_9561(ah)) {
INIT_INI_ARRAY(&ah->iniModesRxGain,
qca956x_1p0_common_wo_xlna_rx_gain_table);
INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
qca956x_1p0_common_wo_xlna_rx_gain_bounds);
} else if (AR_SREV_9580(ah)) } else if (AR_SREV_9580(ah))
INIT_INI_ARRAY(&ah->iniModesRxGain, INIT_INI_ARRAY(&ah->iniModesRxGain,
ar9580_1p0_wo_xlna_rx_gain_table); ar9580_1p0_wo_xlna_rx_gain_table);

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