crypto: ccree - add ahash support
Add CryptoCell async. hash and HMAC support. Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Gilad Ben-Yossef
Herbert Xu
parent
63ee04c8b4
commit
63893811b0
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@ -1,6 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_CRYPTO_DEV_CCREE) := ccree.o
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ccree-y := cc_driver.o cc_buffer_mgr.o cc_request_mgr.o cc_cipher.o cc_ivgen.o cc_sram_mgr.o
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ccree-y := cc_driver.o cc_buffer_mgr.o cc_request_mgr.o cc_cipher.o cc_hash.o cc_ivgen.o cc_sram_mgr.o
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ccree-$(CONFIG_DEBUG_FS) += cc_debugfs.o
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ccree-$(CONFIG_PM) += cc_pm.o
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@ -9,6 +9,7 @@
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#include "cc_buffer_mgr.h"
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#include "cc_lli_defs.h"
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#include "cc_cipher.h"
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#include "cc_hash.h"
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enum dma_buffer_type {
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DMA_NULL_TYPE = -1,
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@ -348,9 +349,33 @@ static int cc_map_sg(struct device *dev, struct scatterlist *sg,
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return 0;
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}
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static int cc_set_hash_buf(struct device *dev, struct ahash_req_ctx *areq_ctx,
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u8 *curr_buff, u32 curr_buff_cnt,
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struct buffer_array *sg_data)
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{
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dev_dbg(dev, " handle curr buff %x set to DLLI\n", curr_buff_cnt);
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/* create sg for the current buffer */
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sg_init_one(areq_ctx->buff_sg, curr_buff, curr_buff_cnt);
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if (dma_map_sg(dev, areq_ctx->buff_sg, 1, DMA_TO_DEVICE) != 1) {
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dev_err(dev, "dma_map_sg() src buffer failed\n");
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return -ENOMEM;
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}
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dev_dbg(dev, "Mapped curr_buff: dma_address=%pad page=%p addr=%pK offset=%u length=%u\n",
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&sg_dma_address(areq_ctx->buff_sg), sg_page(areq_ctx->buff_sg),
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sg_virt(areq_ctx->buff_sg), areq_ctx->buff_sg->offset,
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areq_ctx->buff_sg->length);
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areq_ctx->data_dma_buf_type = CC_DMA_BUF_DLLI;
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areq_ctx->curr_sg = areq_ctx->buff_sg;
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areq_ctx->in_nents = 0;
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/* prepare for case of MLLI */
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cc_add_sg_entry(dev, sg_data, 1, areq_ctx->buff_sg, curr_buff_cnt, 0,
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false, NULL);
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return 0;
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}
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void cc_unmap_cipher_request(struct device *dev, void *ctx,
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unsigned int ivsize, struct scatterlist *src,
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struct scatterlist *dst)
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unsigned int ivsize, struct scatterlist *src,
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struct scatterlist *dst)
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{
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struct cipher_req_ctx *req_ctx = (struct cipher_req_ctx *)ctx;
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@ -472,6 +497,238 @@ int cc_map_cipher_request(struct cc_drvdata *drvdata, void *ctx,
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return rc;
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}
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int cc_map_hash_request_final(struct cc_drvdata *drvdata, void *ctx,
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struct scatterlist *src, unsigned int nbytes,
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bool do_update, gfp_t flags)
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{
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struct ahash_req_ctx *areq_ctx = (struct ahash_req_ctx *)ctx;
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struct device *dev = drvdata_to_dev(drvdata);
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u8 *curr_buff = cc_hash_buf(areq_ctx);
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u32 *curr_buff_cnt = cc_hash_buf_cnt(areq_ctx);
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struct mlli_params *mlli_params = &areq_ctx->mlli_params;
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struct buffer_array sg_data;
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struct buff_mgr_handle *buff_mgr = drvdata->buff_mgr_handle;
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u32 dummy = 0;
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u32 mapped_nents = 0;
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dev_dbg(dev, "final params : curr_buff=%pK curr_buff_cnt=0x%X nbytes = 0x%X src=%pK curr_index=%u\n",
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curr_buff, *curr_buff_cnt, nbytes, src, areq_ctx->buff_index);
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/* Init the type of the dma buffer */
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areq_ctx->data_dma_buf_type = CC_DMA_BUF_NULL;
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mlli_params->curr_pool = NULL;
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sg_data.num_of_buffers = 0;
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areq_ctx->in_nents = 0;
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if (nbytes == 0 && *curr_buff_cnt == 0) {
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/* nothing to do */
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return 0;
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}
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/*TODO: copy data in case that buffer is enough for operation */
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/* map the previous buffer */
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if (*curr_buff_cnt) {
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if (cc_set_hash_buf(dev, areq_ctx, curr_buff, *curr_buff_cnt,
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&sg_data)) {
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return -ENOMEM;
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}
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}
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if (src && nbytes > 0 && do_update) {
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if (cc_map_sg(dev, src, nbytes, DMA_TO_DEVICE,
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&areq_ctx->in_nents, LLI_MAX_NUM_OF_DATA_ENTRIES,
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&dummy, &mapped_nents)) {
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goto unmap_curr_buff;
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}
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if (src && mapped_nents == 1 &&
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areq_ctx->data_dma_buf_type == CC_DMA_BUF_NULL) {
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memcpy(areq_ctx->buff_sg, src,
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sizeof(struct scatterlist));
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areq_ctx->buff_sg->length = nbytes;
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areq_ctx->curr_sg = areq_ctx->buff_sg;
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areq_ctx->data_dma_buf_type = CC_DMA_BUF_DLLI;
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} else {
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areq_ctx->data_dma_buf_type = CC_DMA_BUF_MLLI;
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}
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}
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/*build mlli */
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if (areq_ctx->data_dma_buf_type == CC_DMA_BUF_MLLI) {
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mlli_params->curr_pool = buff_mgr->mlli_buffs_pool;
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/* add the src data to the sg_data */
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cc_add_sg_entry(dev, &sg_data, areq_ctx->in_nents, src, nbytes,
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0, true, &areq_ctx->mlli_nents);
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if (cc_generate_mlli(dev, &sg_data, mlli_params, flags))
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goto fail_unmap_din;
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}
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/* change the buffer index for the unmap function */
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areq_ctx->buff_index = (areq_ctx->buff_index ^ 1);
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dev_dbg(dev, "areq_ctx->data_dma_buf_type = %s\n",
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cc_dma_buf_type(areq_ctx->data_dma_buf_type));
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return 0;
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fail_unmap_din:
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dma_unmap_sg(dev, src, areq_ctx->in_nents, DMA_TO_DEVICE);
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unmap_curr_buff:
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if (*curr_buff_cnt)
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dma_unmap_sg(dev, areq_ctx->buff_sg, 1, DMA_TO_DEVICE);
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return -ENOMEM;
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}
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int cc_map_hash_request_update(struct cc_drvdata *drvdata, void *ctx,
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struct scatterlist *src, unsigned int nbytes,
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unsigned int block_size, gfp_t flags)
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{
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struct ahash_req_ctx *areq_ctx = (struct ahash_req_ctx *)ctx;
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struct device *dev = drvdata_to_dev(drvdata);
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u8 *curr_buff = cc_hash_buf(areq_ctx);
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u32 *curr_buff_cnt = cc_hash_buf_cnt(areq_ctx);
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u8 *next_buff = cc_next_buf(areq_ctx);
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u32 *next_buff_cnt = cc_next_buf_cnt(areq_ctx);
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struct mlli_params *mlli_params = &areq_ctx->mlli_params;
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unsigned int update_data_len;
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u32 total_in_len = nbytes + *curr_buff_cnt;
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struct buffer_array sg_data;
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struct buff_mgr_handle *buff_mgr = drvdata->buff_mgr_handle;
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unsigned int swap_index = 0;
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u32 dummy = 0;
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u32 mapped_nents = 0;
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dev_dbg(dev, " update params : curr_buff=%pK curr_buff_cnt=0x%X nbytes=0x%X src=%pK curr_index=%u\n",
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curr_buff, *curr_buff_cnt, nbytes, src, areq_ctx->buff_index);
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/* Init the type of the dma buffer */
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areq_ctx->data_dma_buf_type = CC_DMA_BUF_NULL;
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mlli_params->curr_pool = NULL;
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areq_ctx->curr_sg = NULL;
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sg_data.num_of_buffers = 0;
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areq_ctx->in_nents = 0;
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if (total_in_len < block_size) {
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dev_dbg(dev, " less than one block: curr_buff=%pK *curr_buff_cnt=0x%X copy_to=%pK\n",
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curr_buff, *curr_buff_cnt, &curr_buff[*curr_buff_cnt]);
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areq_ctx->in_nents =
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cc_get_sgl_nents(dev, src, nbytes, &dummy, NULL);
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sg_copy_to_buffer(src, areq_ctx->in_nents,
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&curr_buff[*curr_buff_cnt], nbytes);
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*curr_buff_cnt += nbytes;
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return 1;
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}
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/* Calculate the residue size*/
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*next_buff_cnt = total_in_len & (block_size - 1);
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/* update data len */
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update_data_len = total_in_len - *next_buff_cnt;
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dev_dbg(dev, " temp length : *next_buff_cnt=0x%X update_data_len=0x%X\n",
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*next_buff_cnt, update_data_len);
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/* Copy the new residue to next buffer */
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if (*next_buff_cnt) {
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dev_dbg(dev, " handle residue: next buff %pK skip data %u residue %u\n",
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next_buff, (update_data_len - *curr_buff_cnt),
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*next_buff_cnt);
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cc_copy_sg_portion(dev, next_buff, src,
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(update_data_len - *curr_buff_cnt),
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nbytes, CC_SG_TO_BUF);
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/* change the buffer index for next operation */
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swap_index = 1;
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}
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if (*curr_buff_cnt) {
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if (cc_set_hash_buf(dev, areq_ctx, curr_buff, *curr_buff_cnt,
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&sg_data)) {
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return -ENOMEM;
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}
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/* change the buffer index for next operation */
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swap_index = 1;
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}
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if (update_data_len > *curr_buff_cnt) {
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if (cc_map_sg(dev, src, (update_data_len - *curr_buff_cnt),
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DMA_TO_DEVICE, &areq_ctx->in_nents,
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LLI_MAX_NUM_OF_DATA_ENTRIES, &dummy,
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&mapped_nents)) {
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goto unmap_curr_buff;
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}
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if (mapped_nents == 1 &&
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areq_ctx->data_dma_buf_type == CC_DMA_BUF_NULL) {
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/* only one entry in the SG and no previous data */
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memcpy(areq_ctx->buff_sg, src,
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sizeof(struct scatterlist));
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areq_ctx->buff_sg->length = update_data_len;
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areq_ctx->data_dma_buf_type = CC_DMA_BUF_DLLI;
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areq_ctx->curr_sg = areq_ctx->buff_sg;
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} else {
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areq_ctx->data_dma_buf_type = CC_DMA_BUF_MLLI;
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}
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}
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if (areq_ctx->data_dma_buf_type == CC_DMA_BUF_MLLI) {
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mlli_params->curr_pool = buff_mgr->mlli_buffs_pool;
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/* add the src data to the sg_data */
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cc_add_sg_entry(dev, &sg_data, areq_ctx->in_nents, src,
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(update_data_len - *curr_buff_cnt), 0, true,
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&areq_ctx->mlli_nents);
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if (cc_generate_mlli(dev, &sg_data, mlli_params, flags))
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goto fail_unmap_din;
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}
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areq_ctx->buff_index = (areq_ctx->buff_index ^ swap_index);
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return 0;
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fail_unmap_din:
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dma_unmap_sg(dev, src, areq_ctx->in_nents, DMA_TO_DEVICE);
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unmap_curr_buff:
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if (*curr_buff_cnt)
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dma_unmap_sg(dev, areq_ctx->buff_sg, 1, DMA_TO_DEVICE);
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return -ENOMEM;
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}
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void cc_unmap_hash_request(struct device *dev, void *ctx,
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struct scatterlist *src, bool do_revert)
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{
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struct ahash_req_ctx *areq_ctx = (struct ahash_req_ctx *)ctx;
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u32 *prev_len = cc_next_buf_cnt(areq_ctx);
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/*In case a pool was set, a table was
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*allocated and should be released
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*/
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if (areq_ctx->mlli_params.curr_pool) {
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dev_dbg(dev, "free MLLI buffer: dma=%pad virt=%pK\n",
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&areq_ctx->mlli_params.mlli_dma_addr,
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areq_ctx->mlli_params.mlli_virt_addr);
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dma_pool_free(areq_ctx->mlli_params.curr_pool,
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areq_ctx->mlli_params.mlli_virt_addr,
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areq_ctx->mlli_params.mlli_dma_addr);
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}
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if (src && areq_ctx->in_nents) {
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dev_dbg(dev, "Unmapped sg src: virt=%pK dma=%pad len=0x%X\n",
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sg_virt(src), &sg_dma_address(src), sg_dma_len(src));
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dma_unmap_sg(dev, src,
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areq_ctx->in_nents, DMA_TO_DEVICE);
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}
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if (*prev_len) {
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dev_dbg(dev, "Unmapped buffer: areq_ctx->buff_sg=%pK dma=%pad len 0x%X\n",
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sg_virt(areq_ctx->buff_sg),
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&sg_dma_address(areq_ctx->buff_sg),
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sg_dma_len(areq_ctx->buff_sg));
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dma_unmap_sg(dev, areq_ctx->buff_sg, 1, DMA_TO_DEVICE);
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if (!do_revert) {
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/* clean the previous data length for update
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* operation
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*/
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*prev_len = 0;
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} else {
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areq_ctx->buff_index ^= 1;
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}
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}
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}
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int cc_buffer_mgr_init(struct cc_drvdata *drvdata)
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{
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struct buff_mgr_handle *buff_mgr_handle;
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@ -20,6 +20,7 @@
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#include "cc_buffer_mgr.h"
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#include "cc_debugfs.h"
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#include "cc_cipher.h"
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#include "cc_hash.h"
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#include "cc_ivgen.h"
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#include "cc_sram_mgr.h"
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#include "cc_pm.h"
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@ -286,8 +287,17 @@ static int init_cc_resources(struct platform_device *plat_dev)
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goto post_ivgen_err;
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}
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/* hash must be allocated before aead since hash exports APIs */
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rc = cc_hash_alloc(new_drvdata);
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if (rc) {
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dev_err(dev, "cc_hash_alloc failed\n");
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goto post_cipher_err;
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}
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return 0;
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post_cipher_err:
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cc_cipher_free(new_drvdata);
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post_ivgen_err:
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cc_ivgen_fini(new_drvdata);
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post_power_mgr_err:
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@ -318,6 +328,7 @@ static void cleanup_cc_resources(struct platform_device *plat_dev)
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struct cc_drvdata *drvdata =
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(struct cc_drvdata *)platform_get_drvdata(plat_dev);
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cc_hash_free(drvdata);
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cc_cipher_free(drvdata);
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cc_ivgen_fini(drvdata);
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cc_pm_fini(drvdata);
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@ -406,6 +417,8 @@ static int __init ccree_init(void)
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{
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int ret;
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cc_hash_global_init();
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ret = cc_debugfs_global_init();
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if (ret)
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return ret;
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@ -113,6 +113,7 @@ struct cc_drvdata {
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cc_sram_addr_t mlli_sram_addr;
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void *buff_mgr_handle;
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void *cipher_handle;
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void *hash_handle;
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void *request_mgr_handle;
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void *ivgen_handle;
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void *sram_mgr_handle;
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,113 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2012-2018 ARM Limited or its affiliates. */
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/* \file cc_hash.h
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* ARM CryptoCell Hash Crypto API
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*/
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#ifndef __CC_HASH_H__
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#define __CC_HASH_H__
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#include "cc_buffer_mgr.h"
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#define HMAC_IPAD_CONST 0x36363636
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#define HMAC_OPAD_CONST 0x5C5C5C5C
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#if (CC_DEV_SHA_MAX > 256)
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#define HASH_LEN_SIZE 16
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#define CC_MAX_HASH_DIGEST_SIZE SHA512_DIGEST_SIZE
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#define CC_MAX_HASH_BLCK_SIZE SHA512_BLOCK_SIZE
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#else
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#define HASH_LEN_SIZE 8
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#define CC_MAX_HASH_DIGEST_SIZE SHA256_DIGEST_SIZE
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#define CC_MAX_HASH_BLCK_SIZE SHA256_BLOCK_SIZE
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#endif
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#define XCBC_MAC_K1_OFFSET 0
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#define XCBC_MAC_K2_OFFSET 16
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#define XCBC_MAC_K3_OFFSET 32
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#define CC_EXPORT_MAGIC 0xC2EE1070U
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/* this struct was taken from drivers/crypto/nx/nx-aes-xcbc.c and it is used
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* for xcbc/cmac statesize
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*/
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struct aeshash_state {
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u8 state[AES_BLOCK_SIZE];
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unsigned int count;
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u8 buffer[AES_BLOCK_SIZE];
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};
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/* ahash state */
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struct ahash_req_ctx {
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u8 buffers[2][CC_MAX_HASH_BLCK_SIZE] ____cacheline_aligned;
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u8 digest_result_buff[CC_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned;
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u8 digest_buff[CC_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned;
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u8 opad_digest_buff[CC_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned;
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u8 digest_bytes_len[HASH_LEN_SIZE] ____cacheline_aligned;
|
||||
struct async_gen_req_ctx gen_ctx ____cacheline_aligned;
|
||||
enum cc_req_dma_buf_type data_dma_buf_type;
|
||||
dma_addr_t opad_digest_dma_addr;
|
||||
dma_addr_t digest_buff_dma_addr;
|
||||
dma_addr_t digest_bytes_len_dma_addr;
|
||||
dma_addr_t digest_result_dma_addr;
|
||||
u32 buf_cnt[2];
|
||||
u32 buff_index;
|
||||
u32 xcbc_count; /* count xcbc update operatations */
|
||||
struct scatterlist buff_sg[2];
|
||||
struct scatterlist *curr_sg;
|
||||
u32 in_nents;
|
||||
u32 mlli_nents;
|
||||
struct mlli_params mlli_params;
|
||||
};
|
||||
|
||||
static inline u32 *cc_hash_buf_cnt(struct ahash_req_ctx *state)
|
||||
{
|
||||
return &state->buf_cnt[state->buff_index];
|
||||
}
|
||||
|
||||
static inline u8 *cc_hash_buf(struct ahash_req_ctx *state)
|
||||
{
|
||||
return state->buffers[state->buff_index];
|
||||
}
|
||||
|
||||
static inline u32 *cc_next_buf_cnt(struct ahash_req_ctx *state)
|
||||
{
|
||||
return &state->buf_cnt[state->buff_index ^ 1];
|
||||
}
|
||||
|
||||
static inline u8 *cc_next_buf(struct ahash_req_ctx *state)
|
||||
{
|
||||
return state->buffers[state->buff_index ^ 1];
|
||||
}
|
||||
|
||||
int cc_hash_alloc(struct cc_drvdata *drvdata);
|
||||
int cc_init_hash_sram(struct cc_drvdata *drvdata);
|
||||
int cc_hash_free(struct cc_drvdata *drvdata);
|
||||
|
||||
/*!
|
||||
* Gets the initial digest length
|
||||
*
|
||||
* \param drvdata
|
||||
* \param mode The Hash mode. Supported modes:
|
||||
* MD5/SHA1/SHA224/SHA256/SHA384/SHA512
|
||||
*
|
||||
* \return u32 returns the address of the initial digest length in SRAM
|
||||
*/
|
||||
cc_sram_addr_t
|
||||
cc_digest_len_addr(void *drvdata, u32 mode);
|
||||
|
||||
/*!
|
||||
* Gets the address of the initial digest in SRAM
|
||||
* according to the given hash mode
|
||||
*
|
||||
* \param drvdata
|
||||
* \param mode The Hash mode. Supported modes:
|
||||
* MD5/SHA1/SHA224/SHA256/SHA384/SHA512
|
||||
*
|
||||
* \return u32 The address of the initial digest in SRAM
|
||||
*/
|
||||
cc_sram_addr_t cc_larval_digest_addr(void *drvdata, u32 mode);
|
||||
|
||||
void cc_hash_global_init(void);
|
||||
|
||||
#endif /*__CC_HASH_H__*/
|
||||
|
|
@ -9,6 +9,7 @@
|
|||
#include "cc_request_mgr.h"
|
||||
#include "cc_sram_mgr.h"
|
||||
#include "cc_ivgen.h"
|
||||
#include "cc_hash.h"
|
||||
#include "cc_pm.h"
|
||||
|
||||
#define POWER_DOWN_ENABLE 0x01
|
||||
|
|
@ -61,6 +62,9 @@ int cc_pm_resume(struct device *dev)
|
|||
return rc;
|
||||
}
|
||||
|
||||
/* must be after the queue resuming as it uses the HW queue*/
|
||||
cc_init_hash_sram(drvdata);
|
||||
|
||||
cc_init_iv_sram(drvdata);
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue