iio: adc: stm32: introduce compatible data cfg
Prepare support for stm32h7 adc variant by introducing compatible configuration data. Move STM32F4 specific stuff to compatible data structure: - registers & bit fields - input channels data - start/stop procedures - trigger definitions Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
This commit is contained in:
Fabrice Gasnier
Jonathan Cameron
parent
9fd243c4fb
commit
64ad7f6438
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@ -49,12 +49,39 @@
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/* STM32 F4 maximum analog clock rate (from datasheet) */
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#define STM32F4_ADC_MAX_CLK_RATE 36000000
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/**
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* stm32_adc_common_regs - stm32 common registers, compatible dependent data
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* @csr: common status register offset
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* @eoc1: adc1 end of conversion flag in @csr
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* @eoc2: adc2 end of conversion flag in @csr
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* @eoc3: adc3 end of conversion flag in @csr
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*/
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struct stm32_adc_common_regs {
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u32 csr;
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u32 eoc1_msk;
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u32 eoc2_msk;
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u32 eoc3_msk;
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};
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struct stm32_adc_priv;
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/**
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* stm32_adc_priv_cfg - stm32 core compatible configuration data
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* @regs: common registers for all instances
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* @clk_sel: clock selection routine
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*/
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struct stm32_adc_priv_cfg {
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const struct stm32_adc_common_regs *regs;
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int (*clk_sel)(struct platform_device *, struct stm32_adc_priv *);
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};
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/**
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* struct stm32_adc_priv - stm32 ADC core private data
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* @irq: irq for ADC block
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* @domain: irq domain reference
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* @aclk: clock reference for the analog circuitry
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* @vref: regulator reference
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* @cfg: compatible configuration data
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* @common: common data for all ADC instances
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*/
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struct stm32_adc_priv {
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@ -62,6 +89,7 @@ struct stm32_adc_priv {
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struct irq_domain *domain;
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struct clk *aclk;
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struct regulator *vref;
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const struct stm32_adc_priv_cfg *cfg;
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struct stm32_adc_common common;
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};
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@ -112,6 +140,14 @@ static int stm32f4_adc_clk_sel(struct platform_device *pdev,
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return 0;
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}
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/* STM32F4 common registers definitions */
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static const struct stm32_adc_common_regs stm32f4_adc_common_regs = {
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.csr = STM32F4_ADC_CSR,
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.eoc1_msk = STM32F4_EOC1,
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.eoc2_msk = STM32F4_EOC2,
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.eoc3_msk = STM32F4_EOC3,
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};
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/* ADC common interrupt for all instances */
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static void stm32_adc_irq_handler(struct irq_desc *desc)
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{
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@ -120,15 +156,15 @@ static void stm32_adc_irq_handler(struct irq_desc *desc)
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u32 status;
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chained_irq_enter(chip, desc);
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status = readl_relaxed(priv->common.base + STM32F4_ADC_CSR);
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status = readl_relaxed(priv->common.base + priv->cfg->regs->csr);
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if (status & STM32F4_EOC1)
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if (status & priv->cfg->regs->eoc1_msk)
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generic_handle_irq(irq_find_mapping(priv->domain, 0));
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if (status & STM32F4_EOC2)
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if (status & priv->cfg->regs->eoc2_msk)
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generic_handle_irq(irq_find_mapping(priv->domain, 1));
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if (status & STM32F4_EOC3)
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if (status & priv->cfg->regs->eoc3_msk)
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generic_handle_irq(irq_find_mapping(priv->domain, 2));
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chained_irq_exit(chip, desc);
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@ -194,6 +230,7 @@ static void stm32_adc_irq_remove(struct platform_device *pdev,
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static int stm32_adc_probe(struct platform_device *pdev)
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{
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struct stm32_adc_priv *priv;
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struct device *dev = &pdev->dev;
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struct device_node *np = pdev->dev.of_node;
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struct resource *res;
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int ret;
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@ -205,6 +242,9 @@ static int stm32_adc_probe(struct platform_device *pdev)
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if (!priv)
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return -ENOMEM;
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priv->cfg = (const struct stm32_adc_priv_cfg *)
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of_match_device(dev->driver->of_match_table, dev)->data;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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priv->common.base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(priv->common.base))
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@ -251,7 +291,7 @@ static int stm32_adc_probe(struct platform_device *pdev)
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}
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}
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ret = stm32f4_adc_clk_sel(pdev, priv);
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ret = priv->cfg->clk_sel(pdev, priv);
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if (ret < 0)
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goto err_clk_disable;
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@ -296,9 +336,17 @@ static int stm32_adc_remove(struct platform_device *pdev)
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return 0;
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}
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static const struct stm32_adc_priv_cfg stm32f4_adc_priv_cfg = {
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.regs = &stm32f4_adc_common_regs,
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.clk_sel = stm32f4_adc_clk_sel,
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};
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static const struct of_device_id stm32_adc_of_match[] = {
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{ .compatible = "st,stm32f4-adc-core" },
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{},
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{
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.compatible = "st,stm32f4-adc-core",
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.data = (void *)&stm32f4_adc_priv_cfg
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}, {
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},
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};
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MODULE_DEVICE_TABLE(of, stm32_adc_of_match);
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@ -34,6 +34,7 @@
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include "stm32-adc-core.h"
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@ -132,10 +133,49 @@ struct stm32_adc_regs {
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int shift;
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};
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/**
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* stm32_adc_regspec - stm32 registers definition, compatible dependent data
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* @dr: data register offset
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* @ier_eoc: interrupt enable register & eocie bitfield
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* @isr_eoc: interrupt status register & eoc bitfield
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* @sqr: reference to sequence registers array
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* @exten: trigger control register & bitfield
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* @extsel: trigger selection register & bitfield
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* @res: resolution selection register & bitfield
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*/
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struct stm32_adc_regspec {
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const u32 dr;
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const struct stm32_adc_regs ier_eoc;
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const struct stm32_adc_regs isr_eoc;
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const struct stm32_adc_regs *sqr;
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const struct stm32_adc_regs exten;
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const struct stm32_adc_regs extsel;
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const struct stm32_adc_regs res;
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};
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struct stm32_adc;
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/**
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* stm32_adc_cfg - stm32 compatible configuration data
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* @regs: registers descriptions
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* @adc_info: per instance input channels definitions
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* @trigs: external trigger sources
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* @start_conv: routine to start conversions
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* @stop_conv: routine to stop conversions
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*/
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struct stm32_adc_cfg {
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const struct stm32_adc_regspec *regs;
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const struct stm32_adc_info *adc_info;
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struct stm32_adc_trig_info *trigs;
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void (*start_conv)(struct stm32_adc *, bool dma);
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void (*stop_conv)(struct stm32_adc *);
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};
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/**
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* struct stm32_adc - private data of each ADC IIO instance
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* @common: reference to ADC block common data
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* @offset: ADC instance register offset in ADC block
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* @cfg: compatible configuration data
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* @completion: end of single conversion completion
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* @buffer: data buffer
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* @clk: clock for this adc instance
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@ -153,6 +193,7 @@ struct stm32_adc_regs {
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struct stm32_adc {
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struct stm32_adc_common *common;
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u32 offset;
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const struct stm32_adc_cfg *cfg;
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struct completion completion;
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u16 buffer[STM32_ADC_MAX_SQ];
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struct clk *clk;
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@ -180,8 +221,25 @@ struct stm32_adc_chan_spec {
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const char *name;
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};
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/* Input definitions common for all STM32F4 instances */
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static const struct stm32_adc_chan_spec stm32f4_adc123_channels[] = {
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/**
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* struct stm32_adc_info - stm32 ADC, per instance config data
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* @channels: Reference to stm32 channels spec
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* @max_channels: Number of channels
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* @resolutions: available resolutions
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* @num_res: number of available resolutions
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*/
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struct stm32_adc_info {
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const struct stm32_adc_chan_spec *channels;
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int max_channels;
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const unsigned int *resolutions;
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const unsigned int num_res;
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};
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/*
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* Input definitions common for all instances:
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* stm32f4 can have up to 16 channels
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*/
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static const struct stm32_adc_chan_spec stm32_adc_channels[] = {
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{ IIO_VOLTAGE, 0, "in0" },
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{ IIO_VOLTAGE, 1, "in1" },
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{ IIO_VOLTAGE, 2, "in2" },
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@ -205,6 +263,13 @@ static const unsigned int stm32f4_adc_resolutions[] = {
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12, 10, 8, 6,
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};
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static const struct stm32_adc_info stm32f4_adc_info = {
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.channels = stm32_adc_channels,
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.max_channels = 16,
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.resolutions = stm32f4_adc_resolutions,
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.num_res = ARRAY_SIZE(stm32f4_adc_resolutions),
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};
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/**
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* stm32f4_sq - describe regular sequence registers
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* - L: sequence len (register & bit field)
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@ -252,6 +317,17 @@ static struct stm32_adc_trig_info stm32f4_adc_trigs[] = {
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{}, /* sentinel */
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};
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static const struct stm32_adc_regspec stm32f4_adc_regspec = {
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.dr = STM32F4_ADC_DR,
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.ier_eoc = { STM32F4_ADC_CR1, STM32F4_EOCIE },
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.isr_eoc = { STM32F4_ADC_SR, STM32F4_EOC },
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.sqr = stm32f4_sq,
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.exten = { STM32F4_ADC_CR2, STM32F4_EXTEN_MASK, STM32F4_EXTEN_SHIFT },
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.extsel = { STM32F4_ADC_CR2, STM32F4_EXTSEL_MASK,
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STM32F4_EXTSEL_SHIFT },
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.res = { STM32F4_ADC_CR1, STM32F4_RES_MASK, STM32F4_RES_SHIFT },
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};
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/**
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* STM32 ADC registers access routines
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* @adc: stm32 adc instance
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@ -299,7 +375,8 @@ static void stm32_adc_clr_bits(struct stm32_adc *adc, u32 reg, u32 bits)
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*/
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static void stm32_adc_conv_irq_enable(struct stm32_adc *adc)
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{
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stm32_adc_set_bits(adc, STM32F4_ADC_CR1, STM32F4_EOCIE);
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stm32_adc_set_bits(adc, adc->cfg->regs->ier_eoc.reg,
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adc->cfg->regs->ier_eoc.mask);
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};
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/**
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@ -308,19 +385,22 @@ static void stm32_adc_conv_irq_enable(struct stm32_adc *adc)
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*/
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static void stm32_adc_conv_irq_disable(struct stm32_adc *adc)
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{
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stm32_adc_clr_bits(adc, STM32F4_ADC_CR1, STM32F4_EOCIE);
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stm32_adc_clr_bits(adc, adc->cfg->regs->ier_eoc.reg,
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adc->cfg->regs->ier_eoc.mask);
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}
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static void stm32_adc_set_res(struct stm32_adc *adc)
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{
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u32 val = stm32_adc_readl(adc, STM32F4_ADC_CR1);
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const struct stm32_adc_regs *res = &adc->cfg->regs->res;
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u32 val;
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val = (val & ~STM32F4_RES_MASK) | (adc->res << STM32F4_RES_SHIFT);
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stm32_adc_writel(adc, STM32F4_ADC_CR1, val);
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val = stm32_adc_readl(adc, res->reg);
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val = (val & ~res->mask) | (adc->res << res->shift);
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stm32_adc_writel(adc, res->reg, val);
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}
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/**
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* stm32_adc_start_conv() - Start conversions for regular channels.
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* stm32f4_adc_start_conv() - Start conversions for regular channels.
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* @adc: stm32 adc instance
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* @dma: use dma to transfer conversion result
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*
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@ -329,7 +409,7 @@ static void stm32_adc_set_res(struct stm32_adc *adc)
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* conversions, in IIO buffer modes. Otherwise, use ADC interrupt with direct
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* DR read instead (e.g. read_raw, or triggered buffer mode without DMA).
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*/
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static void stm32_adc_start_conv(struct stm32_adc *adc, bool dma)
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static void stm32f4_adc_start_conv(struct stm32_adc *adc, bool dma)
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{
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stm32_adc_set_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN);
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@ -347,7 +427,7 @@ static void stm32_adc_start_conv(struct stm32_adc *adc, bool dma)
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stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_SWSTART);
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}
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static void stm32_adc_stop_conv(struct stm32_adc *adc)
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static void stm32f4_adc_stop_conv(struct stm32_adc *adc)
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{
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stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, STM32F4_EXTEN_MASK);
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stm32_adc_clr_bits(adc, STM32F4_ADC_SR, STM32F4_STRT);
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@ -371,6 +451,7 @@ static int stm32_adc_conf_scan_seq(struct iio_dev *indio_dev,
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const unsigned long *scan_mask)
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{
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struct stm32_adc *adc = iio_priv(indio_dev);
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const struct stm32_adc_regs *sqr = adc->cfg->regs->sqr;
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const struct iio_chan_spec *chan;
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u32 val, bit;
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int i = 0;
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@ -388,20 +469,20 @@ static int stm32_adc_conf_scan_seq(struct iio_dev *indio_dev,
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dev_dbg(&indio_dev->dev, "%s chan %d to SQ%d\n",
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__func__, chan->channel, i);
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val = stm32_adc_readl(adc, stm32f4_sq[i].reg);
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val &= ~stm32f4_sq[i].mask;
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val |= chan->channel << stm32f4_sq[i].shift;
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stm32_adc_writel(adc, stm32f4_sq[i].reg, val);
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val = stm32_adc_readl(adc, sqr[i].reg);
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val &= ~sqr[i].mask;
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val |= chan->channel << sqr[i].shift;
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stm32_adc_writel(adc, sqr[i].reg, val);
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}
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if (!i)
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return -EINVAL;
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/* Sequence len */
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val = stm32_adc_readl(adc, stm32f4_sq[0].reg);
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val &= ~stm32f4_sq[0].mask;
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val |= ((i - 1) << stm32f4_sq[0].shift);
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stm32_adc_writel(adc, stm32f4_sq[0].reg, val);
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val = stm32_adc_readl(adc, sqr[0].reg);
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val &= ~sqr[0].mask;
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val |= ((i - 1) << sqr[0].shift);
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stm32_adc_writel(adc, sqr[0].reg, val);
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return 0;
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}
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@ -412,19 +493,21 @@ static int stm32_adc_conf_scan_seq(struct iio_dev *indio_dev,
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*
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* Returns trigger extsel value, if trig matches, -EINVAL otherwise.
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*/
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static int stm32_adc_get_trig_extsel(struct iio_trigger *trig)
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static int stm32_adc_get_trig_extsel(struct iio_dev *indio_dev,
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struct iio_trigger *trig)
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{
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struct stm32_adc *adc = iio_priv(indio_dev);
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int i;
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/* lookup triggers registered by stm32 timer trigger driver */
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for (i = 0; stm32f4_adc_trigs[i].name; i++) {
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for (i = 0; adc->cfg->trigs[i].name; i++) {
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/**
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* Checking both stm32 timer trigger type and trig name
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* should be safe against arbitrary trigger names.
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*/
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if (is_stm32_timer_trigger(trig) &&
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!strcmp(stm32f4_adc_trigs[i].name, trig->name)) {
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return stm32f4_adc_trigs[i].extsel;
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!strcmp(adc->cfg->trigs[i].name, trig->name)) {
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return adc->cfg->trigs[i].extsel;
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}
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}
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@ -449,7 +532,7 @@ static int stm32_adc_set_trig(struct iio_dev *indio_dev,
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int ret;
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if (trig) {
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ret = stm32_adc_get_trig_extsel(trig);
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ret = stm32_adc_get_trig_extsel(indio_dev, trig);
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if (ret < 0)
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return ret;
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@ -459,11 +542,11 @@ static int stm32_adc_set_trig(struct iio_dev *indio_dev,
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}
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spin_lock_irqsave(&adc->lock, flags);
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val = stm32_adc_readl(adc, STM32F4_ADC_CR2);
|
||||
val &= ~(STM32F4_EXTEN_MASK | STM32F4_EXTSEL_MASK);
|
||||
val |= exten << STM32F4_EXTEN_SHIFT;
|
||||
val |= extsel << STM32F4_EXTSEL_SHIFT;
|
||||
stm32_adc_writel(adc, STM32F4_ADC_CR2, val);
|
||||
val = stm32_adc_readl(adc, adc->cfg->regs->exten.reg);
|
||||
val &= ~(adc->cfg->regs->exten.mask | adc->cfg->regs->extsel.mask);
|
||||
val |= exten << adc->cfg->regs->exten.shift;
|
||||
val |= extsel << adc->cfg->regs->extsel.shift;
|
||||
stm32_adc_writel(adc, adc->cfg->regs->exten.reg, val);
|
||||
spin_unlock_irqrestore(&adc->lock, flags);
|
||||
|
||||
return 0;
|
||||
|
|
@ -515,6 +598,7 @@ static int stm32_adc_single_conv(struct iio_dev *indio_dev,
|
|||
int *res)
|
||||
{
|
||||
struct stm32_adc *adc = iio_priv(indio_dev);
|
||||
const struct stm32_adc_regspec *regs = adc->cfg->regs;
|
||||
long timeout;
|
||||
u32 val;
|
||||
int ret;
|
||||
|
|
@ -524,20 +608,20 @@ static int stm32_adc_single_conv(struct iio_dev *indio_dev,
|
|||
adc->bufi = 0;
|
||||
|
||||
/* Program chan number in regular sequence (SQ1) */
|
||||
val = stm32_adc_readl(adc, stm32f4_sq[1].reg);
|
||||
val &= ~stm32f4_sq[1].mask;
|
||||
val |= chan->channel << stm32f4_sq[1].shift;
|
||||
stm32_adc_writel(adc, stm32f4_sq[1].reg, val);
|
||||
val = stm32_adc_readl(adc, regs->sqr[1].reg);
|
||||
val &= ~regs->sqr[1].mask;
|
||||
val |= chan->channel << regs->sqr[1].shift;
|
||||
stm32_adc_writel(adc, regs->sqr[1].reg, val);
|
||||
|
||||
/* Set regular sequence len (0 for 1 conversion) */
|
||||
stm32_adc_clr_bits(adc, stm32f4_sq[0].reg, stm32f4_sq[0].mask);
|
||||
stm32_adc_clr_bits(adc, regs->sqr[0].reg, regs->sqr[0].mask);
|
||||
|
||||
/* Trigger detection disabled (conversion can be launched in SW) */
|
||||
stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, STM32F4_EXTEN_MASK);
|
||||
stm32_adc_clr_bits(adc, regs->exten.reg, regs->exten.mask);
|
||||
|
||||
stm32_adc_conv_irq_enable(adc);
|
||||
|
||||
stm32_adc_start_conv(adc, false);
|
||||
adc->cfg->start_conv(adc, false);
|
||||
|
||||
timeout = wait_for_completion_interruptible_timeout(
|
||||
&adc->completion, STM32_ADC_TIMEOUT);
|
||||
|
|
@ -550,7 +634,7 @@ static int stm32_adc_single_conv(struct iio_dev *indio_dev,
|
|||
ret = IIO_VAL_INT;
|
||||
}
|
||||
|
||||
stm32_adc_stop_conv(adc);
|
||||
adc->cfg->stop_conv(adc);
|
||||
|
||||
stm32_adc_conv_irq_disable(adc);
|
||||
|
||||
|
|
@ -590,11 +674,12 @@ static irqreturn_t stm32_adc_isr(int irq, void *data)
|
|||
{
|
||||
struct stm32_adc *adc = data;
|
||||
struct iio_dev *indio_dev = iio_priv_to_dev(adc);
|
||||
u32 status = stm32_adc_readl(adc, STM32F4_ADC_SR);
|
||||
const struct stm32_adc_regspec *regs = adc->cfg->regs;
|
||||
u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg);
|
||||
|
||||
if (status & STM32F4_EOC) {
|
||||
if (status & regs->isr_eoc.mask) {
|
||||
/* Reading DR also clears EOC status flag */
|
||||
adc->buffer[adc->bufi] = stm32_adc_readw(adc, STM32F4_ADC_DR);
|
||||
adc->buffer[adc->bufi] = stm32_adc_readw(adc, regs->dr);
|
||||
if (iio_buffer_enabled(indio_dev)) {
|
||||
adc->bufi++;
|
||||
if (adc->bufi >= adc->num_conv) {
|
||||
|
|
@ -621,7 +706,7 @@ static irqreturn_t stm32_adc_isr(int irq, void *data)
|
|||
static int stm32_adc_validate_trigger(struct iio_dev *indio_dev,
|
||||
struct iio_trigger *trig)
|
||||
{
|
||||
return stm32_adc_get_trig_extsel(trig) < 0 ? -EINVAL : 0;
|
||||
return stm32_adc_get_trig_extsel(indio_dev, trig) < 0 ? -EINVAL : 0;
|
||||
}
|
||||
|
||||
static int stm32_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val)
|
||||
|
|
@ -799,7 +884,7 @@ static int stm32_adc_buffer_postenable(struct iio_dev *indio_dev)
|
|||
if (!adc->dma_chan)
|
||||
stm32_adc_conv_irq_enable(adc);
|
||||
|
||||
stm32_adc_start_conv(adc, !!adc->dma_chan);
|
||||
adc->cfg->start_conv(adc, !!adc->dma_chan);
|
||||
|
||||
return 0;
|
||||
|
||||
|
|
@ -817,7 +902,7 @@ static int stm32_adc_buffer_predisable(struct iio_dev *indio_dev)
|
|||
struct stm32_adc *adc = iio_priv(indio_dev);
|
||||
int ret;
|
||||
|
||||
stm32_adc_stop_conv(adc);
|
||||
adc->cfg->stop_conv(adc);
|
||||
if (!adc->dma_chan)
|
||||
stm32_adc_conv_irq_disable(adc);
|
||||
|
||||
|
|
@ -895,12 +980,12 @@ static int stm32_adc_of_get_resolution(struct iio_dev *indio_dev)
|
|||
u32 res;
|
||||
|
||||
if (of_property_read_u32(node, "assigned-resolution-bits", &res))
|
||||
res = stm32f4_adc_resolutions[0];
|
||||
res = adc->cfg->adc_info->resolutions[0];
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(stm32f4_adc_resolutions); i++)
|
||||
if (res == stm32f4_adc_resolutions[i])
|
||||
for (i = 0; i < adc->cfg->adc_info->num_res; i++)
|
||||
if (res == adc->cfg->adc_info->resolutions[i])
|
||||
break;
|
||||
if (i >= ARRAY_SIZE(stm32f4_adc_resolutions)) {
|
||||
if (i >= adc->cfg->adc_info->num_res) {
|
||||
dev_err(&indio_dev->dev, "Bad resolution: %u bits\n", res);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
|
@ -926,7 +1011,7 @@ static void stm32_adc_chan_init_one(struct iio_dev *indio_dev,
|
|||
chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
|
||||
chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
|
||||
chan->scan_type.sign = 'u';
|
||||
chan->scan_type.realbits = stm32f4_adc_resolutions[adc->res];
|
||||
chan->scan_type.realbits = adc->cfg->adc_info->resolutions[adc->res];
|
||||
chan->scan_type.storagebits = 16;
|
||||
chan->ext_info = stm32_adc_ext_info;
|
||||
}
|
||||
|
|
@ -934,6 +1019,8 @@ static void stm32_adc_chan_init_one(struct iio_dev *indio_dev,
|
|||
static int stm32_adc_chan_of_init(struct iio_dev *indio_dev)
|
||||
{
|
||||
struct device_node *node = indio_dev->dev.of_node;
|
||||
struct stm32_adc *adc = iio_priv(indio_dev);
|
||||
const struct stm32_adc_info *adc_info = adc->cfg->adc_info;
|
||||
struct property *prop;
|
||||
const __be32 *cur;
|
||||
struct iio_chan_spec *channels;
|
||||
|
|
@ -942,7 +1029,7 @@ static int stm32_adc_chan_of_init(struct iio_dev *indio_dev)
|
|||
|
||||
num_channels = of_property_count_u32_elems(node, "st,adc-channels");
|
||||
if (num_channels < 0 ||
|
||||
num_channels >= ARRAY_SIZE(stm32f4_adc123_channels)) {
|
||||
num_channels >= adc_info->max_channels) {
|
||||
dev_err(&indio_dev->dev, "Bad st,adc-channels?\n");
|
||||
return num_channels < 0 ? num_channels : -EINVAL;
|
||||
}
|
||||
|
|
@ -953,12 +1040,12 @@ static int stm32_adc_chan_of_init(struct iio_dev *indio_dev)
|
|||
return -ENOMEM;
|
||||
|
||||
of_property_for_each_u32(node, "st,adc-channels", prop, cur, val) {
|
||||
if (val >= ARRAY_SIZE(stm32f4_adc123_channels)) {
|
||||
if (val >= adc_info->max_channels) {
|
||||
dev_err(&indio_dev->dev, "Invalid channel %d\n", val);
|
||||
return -EINVAL;
|
||||
}
|
||||
stm32_adc_chan_init_one(indio_dev, &channels[scan_index],
|
||||
&stm32f4_adc123_channels[val],
|
||||
&adc_info->channels[val],
|
||||
scan_index);
|
||||
scan_index++;
|
||||
}
|
||||
|
|
@ -990,7 +1077,7 @@ static int stm32_adc_dma_request(struct iio_dev *indio_dev)
|
|||
/* Configure DMA channel to read data register */
|
||||
memset(&config, 0, sizeof(config));
|
||||
config.src_addr = (dma_addr_t)adc->common->phys_base;
|
||||
config.src_addr += adc->offset + STM32F4_ADC_DR;
|
||||
config.src_addr += adc->offset + adc->cfg->regs->dr;
|
||||
config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
|
||||
|
||||
ret = dmaengine_slave_config(adc->dma_chan, &config);
|
||||
|
|
@ -1011,6 +1098,7 @@ static int stm32_adc_dma_request(struct iio_dev *indio_dev)
|
|||
static int stm32_adc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct iio_dev *indio_dev;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct stm32_adc *adc;
|
||||
int ret;
|
||||
|
||||
|
|
@ -1025,6 +1113,8 @@ static int stm32_adc_probe(struct platform_device *pdev)
|
|||
adc->common = dev_get_drvdata(pdev->dev.parent);
|
||||
spin_lock_init(&adc->lock);
|
||||
init_completion(&adc->completion);
|
||||
adc->cfg = (const struct stm32_adc_cfg *)
|
||||
of_match_device(dev->driver->of_match_table, dev)->data;
|
||||
|
||||
indio_dev->name = dev_name(&pdev->dev);
|
||||
indio_dev->dev.parent = &pdev->dev;
|
||||
|
|
@ -1129,8 +1219,16 @@ static int stm32_adc_remove(struct platform_device *pdev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static const struct stm32_adc_cfg stm32f4_adc_cfg = {
|
||||
.regs = &stm32f4_adc_regspec,
|
||||
.adc_info = &stm32f4_adc_info,
|
||||
.trigs = stm32f4_adc_trigs,
|
||||
.start_conv = stm32f4_adc_start_conv,
|
||||
.stop_conv = stm32f4_adc_stop_conv,
|
||||
};
|
||||
|
||||
static const struct of_device_id stm32_adc_of_match[] = {
|
||||
{ .compatible = "st,stm32f4-adc" },
|
||||
{ .compatible = "st,stm32f4-adc", .data = (void *)&stm32f4_adc_cfg },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, stm32_adc_of_match);
|
||||
|
|
|
|||
Loading…
Reference in New Issue