ARM: New SoC family support
Two new SoC families are added this time. Sugaya Taichi submitted support for the Milbeaut SoC family from Socionext and explains: "SC2000 is a SoC of the Milbeaut series. equipped with a DSP optimized for computer vision. It also features advanced functionalities such as 360-degree, real-time spherical stitching with multi cameras, image stabilization for without mechanical gimbals, and rolling shutter correction. More detail is below: https://www.socionext.com/en/products/assp/milbeaut/SC2000.html" Interestingly, this one has a history dating back to older chips made by Socionext and previously Matsushita/Panasonic based on their own mn10300 CPU architecture that was removed from the kernel last year. Manivannan Sadhasivam adds support for another SoC family, this is the Bitmain BM1880 chip used in the Sophon Edge TPU developer board. The chip is intended for Deep Learning applications, and comes with dual-core Arm Cortex-A53 to run Linux as well as a RISC-V microcontroller core to control the tensor unit. For the moment, the TPU is not accessible in mainline Linux, so we treat it as a generic Arm SoC. More information is available at https://www.sophon.ai/ Signed-off-by: Arnd Bergmann <arnd@arndb.de> -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCAAGBQJcf9USAAoJEGCrR//JCVIn8M8P/1+wpy+9PZynYOqIZvTAR0Pr wqZD20FIjzbEMBpbSMWpOSxg+KbSuf+K1s+1lF6hAGry5UW8CVgZ7DMQ2DyBZfzN NEcJ1MfchN1AblpD4L76C7PzLR4ZbmNHmXaGX5KQ3ItXFX50TI+PBNdlRMho1y2P NGD8SLD1K+erfGyx6CHY+Wf6el25I7tP739HZGvZfMR1SDSKp73fwbjmBBg8vg7/ 2kIwjU7msgtIh4xAgNnZ7+uNUovi04ibDpQnOMta4Urdc9WBJPVQrTmrNJU0loJr bffhrrK4adZgp40gtjajCqPR6F96shyZ2G7nYxe53FGE4whSsMCZuGb5aXJ9OtZq ez0w3Vy16+2uLLA55xVGgcsOv/4pwXnxuVnfw4D5lonU8Q5bbh5pBTVnvV6lFOea IOLaEcfwBCLKMAkZ//eHn9PIGg3RBko4MZniJwb+WLbHXWR+MriQ4+Pb+cvugOAo ky4I9iU/XAmUfJxVC1ShHZrzgz2kEoZXCsX0yqXR1eG4o1Ztbftrs4UOyvTxeqxl lvLXg3b0SDA5QBwQHUxL0G9HTqm4LdMs3lg98kI05gWofz6Bmk1aEi7U4uguhGKf KafuUZ6snVF5KGJAI745Q4IkLKelxjBymLEi+FVKk6y0KAejQXuSMpgXwC1SnIN3 M69uqcDP+ICqCgDbwWCx =HQS8 -----END PGP SIGNATURE----- Merge tag 'armsoc-newsoc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM new SoC family support from Arnd Bergmann: "Two new SoC families are added this time. Sugaya Taichi submitted support for the Milbeaut SoC family from Socionext and explains: "SC2000 is a SoC of the Milbeaut series. equipped with a DSP optimized for computer vision. It also features advanced functionalities such as 360-degree, real-time spherical stitching with multi cameras, image stabilization for without mechanical gimbals, and rolling shutter correction. More detail is below: https://www.socionext.com/en/products/assp/milbeaut/SC2000.html" Interestingly, this one has a history dating back to older chips made by Socionext and previously Matsushita/Panasonic based on their own mn10300 CPU architecture that was removed from the kernel last year. Manivannan Sadhasivam adds support for another SoC family, this is the Bitmain BM1880 chip used in the Sophon Edge TPU developer board. The chip is intended for Deep Learning applications, and comes with dual-core Arm Cortex-A53 to run Linux as well as a RISC-V microcontroller core to control the tensor unit. For the moment, the TPU is not accessible in mainline Linux, so we treat it as a generic Arm SoC. More information is available at https://www.sophon.ai/" * tag 'armsoc-newsoc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: ARM: multi_v7_defconfig: add ARCH_MILBEAUT and ARCH_MILBEAUT_M10V ARM: configs: Add Milbeaut M10V defconfig ARM: dts: milbeaut: Add device tree set for the Milbeaut M10V board clocksource/drivers/timer-milbeaut: Introduce timer for Milbeaut SoCs dt-bindings: timer: Add Milbeaut M10V timer description ARM: milbeaut: Add basic support for Milbeaut m10v SoC dt-bindings: Add documentation for Milbeaut SoCs dt-bindings: arm: Add SMP enable-method for Milbeaut dt-bindings: sram: milbeaut: Add binding for Milbeaut smp-sram MAINTAINERS: Add entry for Bitmain SoC platform arm64: dts: bitmain: Add Sophon Egde board support arm64: dts: bitmain: Add BM1880 SoC support arm64: Add ARCH_BITMAIN platform dt-bindings: arm: Document Bitmain BM1880 SoC
This commit is contained in:
Linus Torvalds
commit
64b1b217f1
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@ -0,0 +1,18 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/bitmain.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Bitmain platform device tree bindings
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maintainers:
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- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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properties:
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compatible:
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items:
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- enum:
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- bitmain,sophon-edge
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- const: bitmain,bm1880
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...
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@ -228,6 +228,7 @@ patternProperties:
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- renesas,r9a06g032-smp
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- rockchip,rk3036-smp
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- rockchip,rk3066-smp
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- socionext,milbeaut-m10v-smp
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- ste,dbx500-smp
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cpu-release-addr:
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|
|
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@ -0,0 +1,22 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/milbeaut.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Milbeaut platforms device tree bindings
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maintainers:
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- Taichi Sugaya <sugaya.taichi@socionext.com>
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- Takao Orito <orito.takao@socionext.com>
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properties:
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$nodename:
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const: '/'
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compatible:
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oneOf:
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- items:
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- enum:
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- socionext,milbeaut-m10v-evb
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- const: socionext,sc2000a
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...
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@ -0,0 +1,24 @@
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Milbeaut SRAM for smp bringup
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Milbeaut SoCs use a part of the sram for the bringup of the secondary cores.
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Once they get powered up in the bootloader, they stay at the specific part
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of the sram.
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Therefore the part needs to be added as the sub-node of mmio-sram.
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Required sub-node properties:
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- compatible : should be "socionext,milbeaut-smp-sram"
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Example:
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sram: sram@0 {
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compatible = "mmio-sram";
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reg = <0x0 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x0 0x10000>;
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smp-sram@f100 {
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compatible = "socionext,milbeaut-smp-sram";
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reg = <0xf100 0x20>;
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};
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};
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@ -0,0 +1,17 @@
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Milbeaut SoCs Timer Controller
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Required properties:
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- compatible : should be "socionext,milbeaut-timer".
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- reg : Specifies base physical address and size of the registers.
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- interrupts : The interrupt of the first timer.
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- clocks: phandle to the input clk.
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|
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Example:
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timer {
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compatible = "socionext,milbeaut-timer";
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reg = <0x1e000050 0x20>
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interrupts = <0 91 4>;
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clocks = <&clk 4>;
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};
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@ -1371,6 +1371,13 @@ F: arch/arm/mach-aspeed/
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F: arch/arm/boot/dts/aspeed-*
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N: aspeed
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ARM/BITMAIN ARCHITECTURE
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M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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F: arch/arm64/boot/dts/bitmain/
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F: Documentation/devicetree/bindings/arm/bitmain.yaml
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|
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ARM/CALXEDA HIGHBANK ARCHITECTURE
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M: Rob Herring <robh@kernel.org>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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|
|
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@ -751,6 +751,8 @@ source "arch/arm/mach-mediatek/Kconfig"
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source "arch/arm/mach-meson/Kconfig"
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source "arch/arm/mach-milbeaut/Kconfig"
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source "arch/arm/mach-mmp/Kconfig"
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|
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source "arch/arm/mach-moxart/Kconfig"
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|
|
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|||
|
|
@ -190,6 +190,7 @@ machine-$(CONFIG_ARCH_MV78XX0) += mv78xx0
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|||
machine-$(CONFIG_ARCH_MVEBU) += mvebu
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machine-$(CONFIG_ARCH_MXC) += imx
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machine-$(CONFIG_ARCH_MEDIATEK) += mediatek
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machine-$(CONFIG_ARCH_MILBEAUT) += milbeaut
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machine-$(CONFIG_ARCH_MXS) += mxs
|
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machine-$(CONFIG_ARCH_NETX) += netx
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machine-$(CONFIG_ARCH_NOMADIK) += nomadik
|
||||
|
|
|
|||
|
|
@ -1246,6 +1246,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
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mt7623n-bananapi-bpi-r2.dtb \
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mt8127-moose.dtb \
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mt8135-evbp1.dtb
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dtb-$(CONFIG_ARCH_MILBEAUT) += milbeaut-m10v-evb.dtb
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dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
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dtb-$(CONFIG_ARCH_ASPEED) += \
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aspeed-ast2500-evb.dtb \
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|
|
|
|||
|
|
@ -0,0 +1,32 @@
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// SPDX-License-Identifier: GPL-2.0
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/* Socionext Milbeaut M10V Evaluation Board */
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/dts-v1/;
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#include "milbeaut-m10v.dtsi"
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/ {
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model = "Socionext M10V EVB";
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compatible = "socionext,milbeaut-m10v-evb", "socionext,sc2000a";
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aliases {
|
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serial0 = &uart1;
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};
|
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|
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chosen {
|
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bootargs = "rootwait earlycon";
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stdout-path = "serial0:115200n8";
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};
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|
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clocks {
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uclk40xi: uclk40xi {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <40000000>;
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};
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0x40000000 0x80000000>;
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};
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||||
|
||||
};
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||||
|
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@ -0,0 +1,95 @@
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// SPDX-License-Identifier: GPL-2.0
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#include <dt-bindings/interrupt-controller/irq.h>
|
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "socionext,sc2000a";
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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|
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cpus {
|
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "socionext,milbeaut-m10v-smp";
|
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cpu@f00 {
|
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf00>;
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};
|
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cpu@f01 {
|
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device_type = "cpu";
|
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compatible = "arm,cortex-a7";
|
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reg = <0xf01>;
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};
|
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cpu@f02 {
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device_type = "cpu";
|
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compatible = "arm,cortex-a7";
|
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reg = <0xf02>;
|
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};
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cpu@f03 {
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device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
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reg = <0xf03>;
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};
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};
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timer { /* The Generic Timer */
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
|
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
|
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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clock-frequency = <40000000>;
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always-on;
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};
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soc {
|
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupt-parent = <&gic>;
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gic: interrupt-controller@1d000000 {
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compatible = "arm,cortex-a7-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x1d001000 0x1000>,
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<0x1d002000 0x1000>; /* CPU I/f base and size */
|
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};
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timer@1e000050 { /* 32-bit Reload Timers */
|
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compatible = "socionext,milbeaut-timer";
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reg = <0x1e000050 0x20>;
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interrupts = <0 91 4>;
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};
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uart1: serial@1e700010 { /* PE4, PE5 */
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/* Enable this as ttyUSI0 */
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compatible = "socionext,milbeaut-usio-uart";
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reg = <0x1e700010 0x10>;
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interrupts = <0 141 0x4>, <0 149 0x4>;
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interrupt-names = "rx", "tx";
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};
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|
||||
};
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|
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sram@0 {
|
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compatible = "mmio-sram";
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reg = <0x0 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x0 0x10000>;
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smp-sram@f100 {
|
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compatible = "socionext,milbeaut-smp-sram";
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reg = <0xf100 0x20>;
|
||||
};
|
||||
};
|
||||
};
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|
|
@ -0,0 +1,119 @@
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|||
CONFIG_SYSVIPC=y
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CONFIG_NO_HZ=y
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CONFIG_HIGH_RES_TIMERS=y
|
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CONFIG_CGROUPS=y
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CONFIG_BLK_DEV_INITRD=y
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CONFIG_EMBEDDED=y
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CONFIG_PERF_EVENTS=y
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CONFIG_ARCH_MILBEAUT=y
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CONFIG_ARCH_MILBEAUT_M10V=y
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CONFIG_ARM_THUMBEE=y
|
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# CONFIG_VDSO is not set
|
||||
# CONFIG_CACHE_L2X0 is not set
|
||||
CONFIG_ARM_ERRATA_430973=y
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CONFIG_ARM_ERRATA_720789=y
|
||||
CONFIG_ARM_ERRATA_754322=y
|
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CONFIG_ARM_ERRATA_754327=y
|
||||
CONFIG_ARM_ERRATA_764369=y
|
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CONFIG_ARM_ERRATA_775420=y
|
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CONFIG_ARM_ERRATA_798181=y
|
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CONFIG_SMP=y
|
||||
# CONFIG_SMP_ON_UP is not set
|
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# CONFIG_ARM_CPU_TOPOLOGY is not set
|
||||
CONFIG_HAVE_ARM_ARCH_TIMER=y
|
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CONFIG_NR_CPUS=16
|
||||
CONFIG_THUMB2_KERNEL=y
|
||||
# CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11 is not set
|
||||
# CONFIG_ARM_PATCH_IDIV is not set
|
||||
CONFIG_HIGHMEM=y
|
||||
CONFIG_FORCE_MAX_ZONEORDER=12
|
||||
CONFIG_SECCOMP=y
|
||||
CONFIG_KEXEC=y
|
||||
CONFIG_EFI=y
|
||||
CONFIG_CPU_FREQ=y
|
||||
CONFIG_CPU_FREQ_STAT=y
|
||||
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
|
||||
CONFIG_CPU_FREQ_GOV_POWERSAVE=m
|
||||
CONFIG_CPU_FREQ_GOV_USERSPACE=m
|
||||
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
|
||||
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
|
||||
CONFIG_CPUFREQ_DT=y
|
||||
CONFIG_QORIQ_CPUFREQ=y
|
||||
CONFIG_CPU_IDLE=y
|
||||
CONFIG_ARM_CPUIDLE=y
|
||||
CONFIG_VFP=y
|
||||
CONFIG_NEON=y
|
||||
CONFIG_KERNEL_MODE_NEON=y
|
||||
CONFIG_EFI_VARS=m
|
||||
CONFIG_EFI_CAPSULE_LOADER=m
|
||||
CONFIG_ARM_CRYPTO=y
|
||||
CONFIG_CRYPTO_SHA1_ARM_NEON=m
|
||||
CONFIG_CRYPTO_SHA1_ARM_CE=m
|
||||
CONFIG_CRYPTO_SHA2_ARM_CE=m
|
||||
CONFIG_CRYPTO_SHA512_ARM=m
|
||||
CONFIG_CRYPTO_AES_ARM=m
|
||||
CONFIG_CRYPTO_AES_ARM_BS=m
|
||||
CONFIG_CRYPTO_AES_ARM_CE=m
|
||||
CONFIG_CRYPTO_GHASH_ARM_CE=m
|
||||
CONFIG_CRYPTO_CRC32_ARM_CE=m
|
||||
CONFIG_CRYPTO_CHACHA20_NEON=m
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_CMDLINE_PARTITION=y
|
||||
CONFIG_CMA=y
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
CONFIG_DMA_CMA=y
|
||||
CONFIG_CMA_SIZE_MBYTES=64
|
||||
CONFIG_OF_OVERLAY=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_SIZE=65536
|
||||
CONFIG_SRAM=y
|
||||
CONFIG_INPUT_FF_MEMLESS=m
|
||||
CONFIG_INPUT_MATRIXKMAP=y
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
CONFIG_SERIO_LIBPS2=y
|
||||
CONFIG_VT_HW_CONSOLE_BINDING=y
|
||||
CONFIG_SERIAL_DEV_BUS=y
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
CONFIG_GPIOLIB=y
|
||||
CONFIG_GPIO_GENERIC_PLATFORM=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_MEDIA_SUPPORT=m
|
||||
CONFIG_MEDIA_CAMERA_SUPPORT=y
|
||||
CONFIG_MEDIA_CONTROLLER=y
|
||||
# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
|
||||
# CONFIG_HID is not set
|
||||
# CONFIG_USB_SUPPORT is not set
|
||||
CONFIG_SYNC_FILE=y
|
||||
# CONFIG_VIRTIO_MENU is not set
|
||||
# CONFIG_IOMMU_SUPPORT is not set
|
||||
CONFIG_SOC_BRCMSTB=y
|
||||
CONFIG_MEMORY=y
|
||||
# CONFIG_ARM_PMU is not set
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_AUTOFS4_FS=y
|
||||
CONFIG_MSDOS_FS=y
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_NTFS_FS=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_TMPFS_POSIX_ACL=y
|
||||
CONFIG_CONFIGFS_FS=y
|
||||
# CONFIG_MISC_FILESYSTEMS is not set
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_NLS_UTF8=y
|
||||
CONFIG_KEYS=y
|
||||
CONFIG_CRYPTO_MANAGER=y
|
||||
# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
|
||||
CONFIG_CRYPTO_SEQIV=m
|
||||
# CONFIG_CRYPTO_ECHAINIV is not set
|
||||
CONFIG_CRYPTO_AES=y
|
||||
# CONFIG_CRYPTO_HW is not set
|
||||
CONFIG_CRC_CCITT=m
|
||||
CONFIG_CRC_ITU_T=m
|
||||
CONFIG_PRINTK_TIME=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
|
|
@ -54,6 +54,8 @@ CONFIG_SOC_VF610=y
|
|||
CONFIG_ARCH_KEYSTONE=y
|
||||
CONFIG_ARCH_MEDIATEK=y
|
||||
CONFIG_ARCH_MESON=y
|
||||
CONFIG_ARCH_MILBEAUT=y
|
||||
CONFIG_ARCH_MILBEAUT_M10V=y
|
||||
CONFIG_ARCH_MVEBU=y
|
||||
CONFIG_MACH_ARMADA_370=y
|
||||
CONFIG_MACH_ARMADA_375=y
|
||||
|
|
|
|||
|
|
@ -0,0 +1,20 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
menuconfig ARCH_MILBEAUT
|
||||
bool "Socionext Milbeaut SoCs"
|
||||
depends on ARCH_MULTI_V7
|
||||
select ARM_GIC
|
||||
help
|
||||
This enables support for Socionext Milbeaut SoCs
|
||||
|
||||
if ARCH_MILBEAUT
|
||||
|
||||
config ARCH_MILBEAUT_M10V
|
||||
bool "Milbeaut SC2000/M10V platform"
|
||||
select ARM_ARCH_TIMER
|
||||
select MILBEAUT_TIMER
|
||||
select PINCTRL
|
||||
select PINCTRL_MILBEAUT
|
||||
help
|
||||
Support for Socionext's MILBEAUT M10V based systems
|
||||
|
||||
endif
|
||||
|
|
@ -0,0 +1 @@
|
|||
obj-$(CONFIG_SMP) += platsmp.o
|
||||
|
|
@ -0,0 +1,143 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright: (C) 2018 Socionext Inc.
|
||||
* Copyright: (C) 2015 Linaro Ltd.
|
||||
*/
|
||||
|
||||
#include <linux/cpu_pm.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/suspend.h>
|
||||
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/cp15.h>
|
||||
#include <asm/idmap.h>
|
||||
#include <asm/smp_plat.h>
|
||||
#include <asm/suspend.h>
|
||||
|
||||
#define M10V_MAX_CPU 4
|
||||
#define KERNEL_UNBOOT_FLAG 0x12345678
|
||||
|
||||
static void __iomem *m10v_smp_base;
|
||||
|
||||
static int m10v_boot_secondary(unsigned int l_cpu, struct task_struct *idle)
|
||||
{
|
||||
unsigned int mpidr, cpu, cluster;
|
||||
|
||||
if (!m10v_smp_base)
|
||||
return -ENXIO;
|
||||
|
||||
mpidr = cpu_logical_map(l_cpu);
|
||||
cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
|
||||
cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
|
||||
|
||||
if (cpu >= M10V_MAX_CPU)
|
||||
return -EINVAL;
|
||||
|
||||
pr_info("%s: cpu %u l_cpu %u cluster %u\n",
|
||||
__func__, cpu, l_cpu, cluster);
|
||||
|
||||
writel(__pa_symbol(secondary_startup), m10v_smp_base + cpu * 4);
|
||||
arch_send_wakeup_ipi_mask(cpumask_of(l_cpu));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void m10v_smp_init(unsigned int max_cpus)
|
||||
{
|
||||
unsigned int mpidr, cpu, cluster;
|
||||
struct device_node *np;
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "socionext,milbeaut-smp-sram");
|
||||
if (!np)
|
||||
return;
|
||||
|
||||
m10v_smp_base = of_iomap(np, 0);
|
||||
if (!m10v_smp_base)
|
||||
return;
|
||||
|
||||
mpidr = read_cpuid_mpidr();
|
||||
cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
|
||||
cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
|
||||
pr_info("MCPM boot on cpu_%u cluster_%u\n", cpu, cluster);
|
||||
|
||||
for (cpu = 0; cpu < M10V_MAX_CPU; cpu++)
|
||||
writel(KERNEL_UNBOOT_FLAG, m10v_smp_base + cpu * 4);
|
||||
}
|
||||
|
||||
static void m10v_cpu_die(unsigned int l_cpu)
|
||||
{
|
||||
gic_cpu_if_down(0);
|
||||
v7_exit_coherency_flush(louis);
|
||||
wfi();
|
||||
}
|
||||
|
||||
static int m10v_cpu_kill(unsigned int l_cpu)
|
||||
{
|
||||
unsigned int mpidr, cpu;
|
||||
|
||||
mpidr = cpu_logical_map(l_cpu);
|
||||
cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
|
||||
|
||||
writel(KERNEL_UNBOOT_FLAG, m10v_smp_base + cpu * 4);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static struct smp_operations m10v_smp_ops __initdata = {
|
||||
.smp_prepare_cpus = m10v_smp_init,
|
||||
.smp_boot_secondary = m10v_boot_secondary,
|
||||
.cpu_die = m10v_cpu_die,
|
||||
.cpu_kill = m10v_cpu_kill,
|
||||
};
|
||||
CPU_METHOD_OF_DECLARE(m10v_smp, "socionext,milbeaut-m10v-smp", &m10v_smp_ops);
|
||||
|
||||
static int m10v_pm_valid(suspend_state_t state)
|
||||
{
|
||||
return (state == PM_SUSPEND_STANDBY) || (state == PM_SUSPEND_MEM);
|
||||
}
|
||||
|
||||
typedef void (*phys_reset_t)(unsigned long);
|
||||
static phys_reset_t phys_reset;
|
||||
|
||||
static int m10v_die(unsigned long arg)
|
||||
{
|
||||
setup_mm_for_reboot();
|
||||
asm("wfi");
|
||||
/* Boot just like a secondary */
|
||||
phys_reset = (phys_reset_t)(unsigned long)virt_to_phys(cpu_reset);
|
||||
phys_reset(virt_to_phys(cpu_resume));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int m10v_pm_enter(suspend_state_t state)
|
||||
{
|
||||
switch (state) {
|
||||
case PM_SUSPEND_STANDBY:
|
||||
asm("wfi");
|
||||
break;
|
||||
case PM_SUSPEND_MEM:
|
||||
cpu_pm_enter();
|
||||
cpu_suspend(0, m10v_die);
|
||||
cpu_pm_exit();
|
||||
break;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct platform_suspend_ops m10v_pm_ops = {
|
||||
.valid = m10v_pm_valid,
|
||||
.enter = m10v_pm_enter,
|
||||
};
|
||||
|
||||
struct clk *m10v_clclk_register(struct device *cpu_dev);
|
||||
|
||||
static int __init m10v_pm_init(void)
|
||||
{
|
||||
if (of_machine_is_compatible("socionext,milbeaut-evb"))
|
||||
suspend_set_ops(&m10v_pm_ops);
|
||||
|
||||
return 0;
|
||||
}
|
||||
late_initcall(m10v_pm_init);
|
||||
|
|
@ -52,6 +52,11 @@ config ARCH_BERLIN
|
|||
help
|
||||
This enables support for Marvell Berlin SoC Family
|
||||
|
||||
config ARCH_BITMAIN
|
||||
bool "Bitmain SoC Platforms"
|
||||
help
|
||||
This enables support for the Bitmain SoC Family.
|
||||
|
||||
config ARCH_BRCMSTB
|
||||
bool "Broadcom Set-Top-Box SoCs"
|
||||
select BRCMSTB_L2_IRQ
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@ subdir-y += amd
|
|||
subdir-y += amlogic
|
||||
subdir-y += apm
|
||||
subdir-y += arm
|
||||
subdir-y += bitmain
|
||||
subdir-y += broadcom
|
||||
subdir-y += cavium
|
||||
subdir-y += exynos
|
||||
|
|
|
|||
|
|
@ -0,0 +1,3 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
dtb-$(CONFIG_ARCH_BITMAIN) += bm1880-sophon-edge.dtb
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2019 Linaro Ltd.
|
||||
* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "bm1880.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "bitmain,sophon-edge", "bitmain,bm1880";
|
||||
model = "Sophon Edge";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart2;
|
||||
serial2 = &uart1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x1 0x00000000 0x0 0x40000000>; // 1GB
|
||||
};
|
||||
|
||||
uart_clk: uart-clk {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <500000000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
clocks = <&uart_clk>;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
clocks = <&uart_clk>;
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
clocks = <&uart_clk>;
|
||||
};
|
||||
|
|
@ -0,0 +1,119 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2019 Linaro Ltd.
|
||||
* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
compatible = "bitmain,bm1880";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
secmon@100000000 {
|
||||
reg = <0x1 0x00000000 0x0 0x20000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
jpu@130000000 {
|
||||
reg = <0x1 0x30000000 0x0 0x08000000>; // 128M
|
||||
no-map;
|
||||
};
|
||||
|
||||
vpu@138000000 {
|
||||
reg = <0x1 0x38000000 0x0 0x08000000>; // 128M
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
gic: interrupt-controller@50001000 {
|
||||
compatible = "arm,gic-400";
|
||||
reg = <0x0 0x50001000 0x0 0x1000>,
|
||||
<0x0 0x50002000 0x0 0x2000>;
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
};
|
||||
|
||||
uart0: serial@58018000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x58018000 0x0 0x2000>;
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@5801A000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x5801a000 0x0 0x2000>;
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@5801C000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x5801c000 0x0 0x2000>;
|
||||
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@5801E000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x5801e000 0x0 0x2000>;
|
||||
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -645,4 +645,13 @@ config GX6605S_TIMER
|
|||
help
|
||||
This option enables support for gx6605s SOC's timer.
|
||||
|
||||
config MILBEAUT_TIMER
|
||||
bool "Milbeaut timer driver" if COMPILE_TEST
|
||||
depends on OF
|
||||
depends on ARM
|
||||
select TIMER_OF
|
||||
select CLKSRC_MMIO
|
||||
help
|
||||
Enables the support for Milbeaut timer driver.
|
||||
|
||||
endmenu
|
||||
|
|
|
|||
|
|
@ -55,6 +55,7 @@ obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o
|
|||
obj-$(CONFIG_CLKSRC_NPS) += timer-nps.o
|
||||
obj-$(CONFIG_OXNAS_RPS_TIMER) += timer-oxnas-rps.o
|
||||
obj-$(CONFIG_OWL_TIMER) += timer-owl.o
|
||||
obj-$(CONFIG_MILBEAUT_TIMER) += timer-milbeaut.o
|
||||
obj-$(CONFIG_SPRD_TIMER) += timer-sprd.o
|
||||
obj-$(CONFIG_NPCM7XX_TIMER) += timer-npcm7xx.o
|
||||
obj-$(CONFIG_RDA_TIMER) += timer-rda.o
|
||||
|
|
|
|||
|
|
@ -0,0 +1,161 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2018 Socionext Inc.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqreturn.h>
|
||||
#include <linux/sched_clock.h>
|
||||
#include "timer-of.h"
|
||||
|
||||
#define MLB_TMR_TMCSR_OFS 0x0
|
||||
#define MLB_TMR_TMR_OFS 0x4
|
||||
#define MLB_TMR_TMRLR1_OFS 0x8
|
||||
#define MLB_TMR_TMRLR2_OFS 0xc
|
||||
#define MLB_TMR_REGSZPCH 0x10
|
||||
|
||||
#define MLB_TMR_TMCSR_OUTL BIT(5)
|
||||
#define MLB_TMR_TMCSR_RELD BIT(4)
|
||||
#define MLB_TMR_TMCSR_INTE BIT(3)
|
||||
#define MLB_TMR_TMCSR_UF BIT(2)
|
||||
#define MLB_TMR_TMCSR_CNTE BIT(1)
|
||||
#define MLB_TMR_TMCSR_TRG BIT(0)
|
||||
|
||||
#define MLB_TMR_TMCSR_CSL_DIV2 0
|
||||
#define MLB_TMR_DIV_CNT 2
|
||||
|
||||
#define MLB_TMR_SRC_CH (1)
|
||||
#define MLB_TMR_EVT_CH (0)
|
||||
|
||||
#define MLB_TMR_SRC_CH_OFS (MLB_TMR_REGSZPCH * MLB_TMR_SRC_CH)
|
||||
#define MLB_TMR_EVT_CH_OFS (MLB_TMR_REGSZPCH * MLB_TMR_EVT_CH)
|
||||
|
||||
#define MLB_TMR_SRC_TMCSR_OFS (MLB_TMR_SRC_CH_OFS + MLB_TMR_TMCSR_OFS)
|
||||
#define MLB_TMR_SRC_TMR_OFS (MLB_TMR_SRC_CH_OFS + MLB_TMR_TMR_OFS)
|
||||
#define MLB_TMR_SRC_TMRLR1_OFS (MLB_TMR_SRC_CH_OFS + MLB_TMR_TMRLR1_OFS)
|
||||
#define MLB_TMR_SRC_TMRLR2_OFS (MLB_TMR_SRC_CH_OFS + MLB_TMR_TMRLR2_OFS)
|
||||
|
||||
#define MLB_TMR_EVT_TMCSR_OFS (MLB_TMR_EVT_CH_OFS + MLB_TMR_TMCSR_OFS)
|
||||
#define MLB_TMR_EVT_TMR_OFS (MLB_TMR_EVT_CH_OFS + MLB_TMR_TMR_OFS)
|
||||
#define MLB_TMR_EVT_TMRLR1_OFS (MLB_TMR_EVT_CH_OFS + MLB_TMR_TMRLR1_OFS)
|
||||
#define MLB_TMR_EVT_TMRLR2_OFS (MLB_TMR_EVT_CH_OFS + MLB_TMR_TMRLR2_OFS)
|
||||
|
||||
#define MLB_TIMER_RATING 500
|
||||
|
||||
static irqreturn_t mlb_timer_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
struct clock_event_device *clk = dev_id;
|
||||
struct timer_of *to = to_timer_of(clk);
|
||||
u32 val;
|
||||
|
||||
val = readl_relaxed(timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
|
||||
val &= ~MLB_TMR_TMCSR_UF;
|
||||
writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
|
||||
|
||||
clk->event_handler(clk);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int mlb_set_state_periodic(struct clock_event_device *clk)
|
||||
{
|
||||
struct timer_of *to = to_timer_of(clk);
|
||||
u32 val = MLB_TMR_TMCSR_CSL_DIV2;
|
||||
|
||||
writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
|
||||
|
||||
writel_relaxed(to->of_clk.period, timer_of_base(to) +
|
||||
MLB_TMR_EVT_TMRLR1_OFS);
|
||||
val |= MLB_TMR_TMCSR_RELD | MLB_TMR_TMCSR_CNTE |
|
||||
MLB_TMR_TMCSR_TRG | MLB_TMR_TMCSR_INTE;
|
||||
writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mlb_set_state_oneshot(struct clock_event_device *clk)
|
||||
{
|
||||
struct timer_of *to = to_timer_of(clk);
|
||||
u32 val = MLB_TMR_TMCSR_CSL_DIV2;
|
||||
|
||||
writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mlb_clkevt_next_event(unsigned long event,
|
||||
struct clock_event_device *clk)
|
||||
{
|
||||
struct timer_of *to = to_timer_of(clk);
|
||||
|
||||
writel_relaxed(event, timer_of_base(to) + MLB_TMR_EVT_TMRLR1_OFS);
|
||||
writel_relaxed(MLB_TMR_TMCSR_CSL_DIV2 |
|
||||
MLB_TMR_TMCSR_CNTE | MLB_TMR_TMCSR_INTE |
|
||||
MLB_TMR_TMCSR_TRG, timer_of_base(to) +
|
||||
MLB_TMR_EVT_TMCSR_OFS);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mlb_config_clock_source(struct timer_of *to)
|
||||
{
|
||||
writel_relaxed(0, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS);
|
||||
writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMR_OFS);
|
||||
writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR1_OFS);
|
||||
writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR2_OFS);
|
||||
writel_relaxed(BIT(4) | BIT(1) | BIT(0), timer_of_base(to) +
|
||||
MLB_TMR_SRC_TMCSR_OFS);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mlb_config_clock_event(struct timer_of *to)
|
||||
{
|
||||
writel_relaxed(0, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct timer_of to = {
|
||||
.flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK,
|
||||
|
||||
.clkevt = {
|
||||
.name = "mlb-clkevt",
|
||||
.rating = MLB_TIMER_RATING,
|
||||
.cpumask = cpu_possible_mask,
|
||||
.features = CLOCK_EVT_FEAT_DYNIRQ | CLOCK_EVT_FEAT_ONESHOT,
|
||||
.set_state_oneshot = mlb_set_state_oneshot,
|
||||
.set_state_periodic = mlb_set_state_periodic,
|
||||
.set_next_event = mlb_clkevt_next_event,
|
||||
},
|
||||
|
||||
.of_irq = {
|
||||
.flags = IRQF_TIMER | IRQF_IRQPOLL,
|
||||
.handler = mlb_timer_interrupt,
|
||||
},
|
||||
};
|
||||
|
||||
static u64 notrace mlb_timer_sched_read(void)
|
||||
{
|
||||
return ~readl_relaxed(timer_of_base(&to) + MLB_TMR_SRC_TMR_OFS);
|
||||
}
|
||||
|
||||
static int __init mlb_timer_init(struct device_node *node)
|
||||
{
|
||||
int ret;
|
||||
unsigned long rate;
|
||||
|
||||
ret = timer_of_init(node, &to);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
rate = timer_of_rate(&to) / MLB_TMR_DIV_CNT;
|
||||
mlb_config_clock_source(&to);
|
||||
clocksource_mmio_init(timer_of_base(&to) + MLB_TMR_SRC_TMR_OFS,
|
||||
node->name, rate, MLB_TIMER_RATING, 32,
|
||||
clocksource_mmio_readl_down);
|
||||
sched_clock_register(mlb_timer_sched_read, 32, rate);
|
||||
mlb_config_clock_event(&to);
|
||||
clockevents_config_and_register(&to.clkevt, timer_of_rate(&to), 15,
|
||||
0xffffffff);
|
||||
return 0;
|
||||
}
|
||||
TIMER_OF_DECLARE(mlb_peritimer, "socionext,milbeaut-timer",
|
||||
mlb_timer_init);
|
||||
Loading…
Reference in New Issue