dmaengine: tegra-apb: Really fix runtime-pm usage
Commitedd3bdbe9d
("dmaengine: tegra-apb: Correct runtime-pm usage") added pm_runtime_get/put() calls to the tegra-apb DMA system suspend callbacks. Runtime PM is disabled during system suspend and so these APIs cannot be used. Fix the suspend handling for the tegra-apb DMA by moving the save and restore of the DMA register context into the runtime PM suspend and resume callbacks, and then use the pm_runtime_force_suspend/resume() APIs to invoke the runtime PM callbacks during system suspend. Fixes:edd3bdbe9d
("dmaengine: tegra-apb: Correct runtime-pm usage") Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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@ -1492,37 +1492,9 @@ static int tegra_dma_remove(struct platform_device *pdev)
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}
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static int tegra_dma_runtime_suspend(struct device *dev)
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{
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struct tegra_dma *tdma = dev_get_drvdata(dev);
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clk_disable_unprepare(tdma->dma_clk);
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return 0;
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}
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static int tegra_dma_runtime_resume(struct device *dev)
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{
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struct tegra_dma *tdma = dev_get_drvdata(dev);
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int ret;
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ret = clk_prepare_enable(tdma->dma_clk);
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if (ret < 0) {
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dev_err(dev, "clk_enable failed: %d\n", ret);
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return ret;
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}
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return 0;
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}
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#ifdef CONFIG_PM_SLEEP
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static int tegra_dma_pm_suspend(struct device *dev)
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{
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struct tegra_dma *tdma = dev_get_drvdata(dev);
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int i;
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int ret;
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/* Enable clock before accessing register */
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ret = pm_runtime_get_sync(dev);
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if (ret < 0)
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return ret;
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tdma->reg_gen = tdma_read(tdma, TEGRA_APBDMA_GENERAL);
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for (i = 0; i < tdma->chip_data->nr_channels; i++) {
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@ -1543,21 +1515,21 @@ static int tegra_dma_pm_suspend(struct device *dev)
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TEGRA_APBDMA_CHAN_WCOUNT);
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}
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/* Disable clock */
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pm_runtime_put(dev);
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clk_disable_unprepare(tdma->dma_clk);
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return 0;
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}
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static int tegra_dma_pm_resume(struct device *dev)
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static int tegra_dma_runtime_resume(struct device *dev)
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{
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struct tegra_dma *tdma = dev_get_drvdata(dev);
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int i;
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int ret;
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int i, ret;
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/* Enable clock before accessing register */
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ret = pm_runtime_get_sync(dev);
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if (ret < 0)
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ret = clk_prepare_enable(tdma->dma_clk);
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if (ret < 0) {
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dev_err(dev, "clk_enable failed: %d\n", ret);
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return ret;
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}
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tdma_write(tdma, TEGRA_APBDMA_GENERAL, tdma->reg_gen);
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tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
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@ -1582,16 +1554,14 @@ static int tegra_dma_pm_resume(struct device *dev)
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(ch_reg->csr & ~TEGRA_APBDMA_CSR_ENB));
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}
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/* Disable clock */
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pm_runtime_put(dev);
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return 0;
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}
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#endif
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static const struct dev_pm_ops tegra_dma_dev_pm_ops = {
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SET_RUNTIME_PM_OPS(tegra_dma_runtime_suspend, tegra_dma_runtime_resume,
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NULL)
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SET_SYSTEM_SLEEP_PM_OPS(tegra_dma_pm_suspend, tegra_dma_pm_resume)
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SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
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pm_runtime_force_resume)
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};
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static const struct of_device_id tegra_dma_of_match[] = {
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