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ARM: SoC fixes for 4.13 

This comes a bit later than I planned, and as a consequence is a larger
 than it should be.
 
 Most of the changes are devicetree fixes, across lots of platforms:
 Renesas, Samsung Exynos, Marvell EBU, TI OMAP, Rockchips, Amlogic Meson,
 Sigma Desings Tango, Allwinner SUNxi and TI Davinci.
 
 Also across many platforms, I applied an older series of simple randconfig
 build fixes. This includes making the CONFIG_MTD_XIP option compile again,
 which had been broken for many years and probably has not been missed, but
 it felt wrong to just remove it completely.
 
 The only other changes are:
 
  - We enable HWSPINLOCK in defconfig to get some Qualcomm boards
    to work out of the box.
 
  - A few regression fixes for Texas Instruments OMAP2+.
 
  - A boot regression fix for the Renesas regulator quirk.
 
  - A suspend/resume fix for Uniphier SoCs, fixing the resume of the
    system bus.
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Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Arnd Bergmann:
 "This comes a bit later than I planned, and as a consequence is a
  larger than it should be.

  Most of the changes are devicetree fixes, across lots of platforms:
  Renesas, Samsung Exynos, Marvell EBU, TI OMAP, Rockchips, Amlogic
  Meson, Sigma Desings Tango, Allwinner SUNxi and TI Davinci.

  Also across many platforms, I applied an older series of simple
  randconfig build fixes. This includes making the CONFIG_MTD_XIP option
  compile again, which had been broken for many years and probably has
  not been missed, but it felt wrong to just remove it completely.

  The only other changes are:

   - We enable HWSPINLOCK in defconfig to get some Qualcomm boards to
     work out of the box.

   - A few regression fixes for Texas Instruments OMAP2+.

   - A boot regression fix for the Renesas regulator quirk.

   - A suspend/resume fix for Uniphier SoCs, fixing the resume of the
     system bus"

* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (43 commits)
  ARM: dts: tango4: Request RGMII RX and TX clock delays
  bus: uniphier-system-bus: set up registers when resuming
  ARM64: dts: marvell: armada-37xx: Fix the number of GPIO on south bridge
  ARM: shmobile: rcar-gen2: Fix deadlock in regulator quirk
  arm64: defconfig: enable missing HWSPINLOCK
  ARM: pxa: select both FB and FB_W100 for eseries
  ARM: ixp4xx: fix ioport_unmap definition
  ARM: ep93xx: use ARM_PATCH_PHYS_VIRT correctly
  ARM: mmp: mark usb_dma_mask as __maybe_unused
  ARM: omap2: mark unused functions as __maybe_unused
  ARM: omap1: avoid unused variable warning
  ARM: sirf: mark sirfsoc_init_late as __maybe_unused
  ARM: ixp4xx: use normal prototype for {read,write}s{b,w,l}
  ARM: omap1/ams-delta: warn about failed regulator enable
  ARM: rpc: rename RAM_SIZE macro
  ARM: w90x900: normalize clk API
  ARM: ep93xx: normalize clk API
  ARM: dts: sun8i: a83t: Switch to CCU device tree binding macros
  arm64: allwinner: sun50i-a64: Correct emac register size
  ARM: dts: sunxi: h3/h5: Correct emac register size
  ...
This commit is contained in:
Linus Torvalds 2017-08-04 15:12:15 -07:00
parent b3c6858fb1 41c454fa0e
commit 65f4740e72
46 changed files with 372 additions and 103 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
View File

@ -40,7 +40,7 @@ Optional properties:
Example for a Mali-T760:
gpu@ffa30000 {
compatible = "rockchip,rk3288-mali", "arm,mali-t760", "arm,mali-midgard";
compatible = "rockchip,rk3288-mali", "arm,mali-t760";
reg = <0xffa30000 0x10000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,

2
arch/arm/Kconfig
View File

@ -380,7 +380,7 @@ config ARCH_EP93XX
bool "EP93xx-based"
select ARCH_HAS_HOLES_MEMORYMODEL
select ARM_AMBA
select ARM_PATCH_PHYS_VIRT
imply ARM_PATCH_PHYS_VIRT
select ARM_VIC
select AUTO_ZRELADDR
select CLKDEV_LOOKUP

4
arch/arm/boot/dts/armada-388-gp.dts
View File

@ -75,7 +75,7 @@ expander0: pca9555@20 {
pinctrl-names = "default";
pinctrl-0 = <&pca0_pins>;
interrupt-parent = <&gpio0>;
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@ -87,7 +87,7 @@ expander1: pca9555@21 {
compatible = "nxp,pca9555";
pinctrl-names = "default";
interrupt-parent = <&gpio0>;
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;

21
arch/arm/boot/dts/da850-evm.dts
View File

@ -301,25 +301,4 @@ &vpif {
pinctrl-names = "default";
pinctrl-0 = <&vpif_capture_pins>, <&vpif_display_pins>;
status = "okay";
/* VPIF capture port */
port@0 {
vpif_input_ch0: endpoint@0 {
reg = <0>;
bus-width = <8>;
};
vpif_input_ch1: endpoint@1 {
reg = <1>;
bus-width = <8>;
data-shift = <8>;
};
};
/* VPIF display port */
port@1 {
vpif_output_ch0: endpoint {
bus-width = <8>;
};
};
};

7
arch/arm/boot/dts/da850-lcdk.dts
View File

@ -318,11 +318,4 @@ &vpif {
pinctrl-names = "default";
pinctrl-0 = <&vpif_capture_pins>;
status = "okay";
/* VPIF capture port */
port {
vpif_ch0: endpoint {
bus-width = <8>;
};
};
};

34
arch/arm/boot/dts/dm8168-evm.dts
View File

@ -68,6 +68,34 @@ usb1_pins: pinmux_usb1_pins {
DM816X_IOPAD(0x0d08, MUX_MODE0) /* USB1_DRVVBUS */
>;
};
nandflash_pins: nandflash_pins {
pinctrl-single,pins = <
DM816X_IOPAD(0x0b38, PULL_UP | MUX_MODE0) /* PINCTRL207 GPMC_CS0*/
DM816X_IOPAD(0x0b60, PULL_ENA | MUX_MODE0) /* PINCTRL217 GPMC_ADV_ALE */
DM816X_IOPAD(0x0b54, PULL_UP | PULL_ENA | MUX_MODE0) /* PINCTRL214 GPMC_OE_RE */
DM816X_IOPAD(0x0b58, PULL_ENA | MUX_MODE0) /* PINCTRL215 GPMC_BE0_CLE */
DM816X_IOPAD(0x0b50, PULL_UP | MUX_MODE0) /* PINCTRL213 GPMC_WE */
DM816X_IOPAD(0x0b6c, MUX_MODE0) /* PINCTRL220 GPMC_WAIT */
DM816X_IOPAD(0x0be4, PULL_ENA | MUX_MODE0) /* PINCTRL250 GPMC_CLK */
DM816X_IOPAD(0x0ba4, MUX_MODE0) /* PINCTRL234 GPMC_D0 */
DM816X_IOPAD(0x0ba8, MUX_MODE0) /* PINCTRL234 GPMC_D1 */
DM816X_IOPAD(0x0bac, MUX_MODE0) /* PINCTRL234 GPMC_D2 */
DM816X_IOPAD(0x0bb0, MUX_MODE0) /* PINCTRL234 GPMC_D3 */
DM816X_IOPAD(0x0bb4, MUX_MODE0) /* PINCTRL234 GPMC_D4 */
DM816X_IOPAD(0x0bb8, MUX_MODE0) /* PINCTRL234 GPMC_D5 */
DM816X_IOPAD(0x0bbc, MUX_MODE0) /* PINCTRL234 GPMC_D6 */
DM816X_IOPAD(0x0bc0, MUX_MODE0) /* PINCTRL234 GPMC_D7 */
DM816X_IOPAD(0x0bc4, MUX_MODE0) /* PINCTRL234 GPMC_D8 */
DM816X_IOPAD(0x0bc8, MUX_MODE0) /* PINCTRL234 GPMC_D9 */
DM816X_IOPAD(0x0bcc, MUX_MODE0) /* PINCTRL234 GPMC_D10 */
DM816X_IOPAD(0x0bd0, MUX_MODE0) /* PINCTRL234 GPMC_D11 */
DM816X_IOPAD(0x0bd4, MUX_MODE0) /* PINCTRL234 GPMC_D12 */
DM816X_IOPAD(0x0bd8, MUX_MODE0) /* PINCTRL234 GPMC_D13 */
DM816X_IOPAD(0x0bdc, MUX_MODE0) /* PINCTRL234 GPMC_D14 */
DM816X_IOPAD(0x0be0, MUX_MODE0) /* PINCTRL234 GPMC_D15 */
>;
};
};
&i2c1 {
@ -90,6 +118,8 @@ extgpio1: pcf8575@20 {
&gpmc {
ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */
pinctrl-names = "default";
pinctrl-0 = <&nandflash_pins>;
nand@0,0 {
compatible = "ti,omap2-nand";
@ -98,9 +128,11 @@ nand@0,0 {
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
#address-cells = <1>;
#size-cells = <1>;
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <16>;
gpmc,device-width = <2>;
gpmc,sync-clk-ps = <0>;
@ -164,7 +196,7 @@ &mmc1 {
vmmc-supply = <&vmmcsd_fixed>;
bus-width = <4>;
cd-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
};
/* At least dm8168-evm rev c won't support multipoint, later may */

2
arch/arm/boot/dts/dm816x.dtsi
View File

@ -145,7 +145,7 @@ edma: edma@49000000 {
};
elm: elm@48080000 {
compatible = "ti,816-elm";
compatible = "ti,am3352-elm";
ti,hwmods = "elm";
reg = <0x48080000 0x2000>;
interrupts = <4>;

4
arch/arm/boot/dts/dra71-evm.dts
View File

@ -190,7 +190,7 @@ dp83867_0: ethernet-phy@2 {
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
ti,impedance-control = <0x1f>;
ti,min-output-impedance;
};
dp83867_1: ethernet-phy@3 {
@ -198,7 +198,7 @@ dp83867_1: ethernet-phy@3 {
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
ti,impedance-control = <0x1f>;
ti,min-output-impedance;
};
};

3
arch/arm/boot/dts/exynos4.dtsi
View File

@ -59,6 +59,9 @@ clock_audss: clock-controller@03810000 {
compatible = "samsung,exynos4210-audss-clock";
reg = <0x03810000 0x0C>;
#clock-cells = <1>;
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
<&clock CLK_SCLK_AUDIO0>, <&clock CLK_SCLK_AUDIO0>;
clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
};
i2s0: i2s@03830000 {

4
arch/arm/boot/dts/rk3288.dtsi
View File

@ -1126,8 +1126,8 @@ hdmi_in_vopl: endpoint@1 {
};
};
gpu: mali@ffa30000 {
compatible = "rockchip,rk3288-mali", "arm,mali-t760", "arm,mali-midgard";
gpu: gpu@ffa30000 {
compatible = "rockchip,rk3288-mali", "arm,mali-t760";
reg = <0xffa30000 0x10000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,

16
arch/arm/boot/dts/sun8i-a83t.dtsi
View File

@ -44,7 +44,9 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/sun8i-a83t-ccu.h>
#include <dt-bindings/clock/sun8i-r-ccu.h>
#include <dt-bindings/reset/sun8i-a83t-ccu.h>
/ {
interrupt-parent = <&gic>;
@ -175,8 +177,8 @@ dma: dma-controller@1c02000 {
compatible = "allwinner,sun8i-a83t-dma";
reg = <0x01c02000 0x1000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu 21>;
resets = <&ccu 7>;
clocks = <&ccu CLK_BUS_DMA>;
resets = <&ccu RST_BUS_DMA>;
#dma-cells = <1>;
};
@ -195,7 +197,7 @@ pio: pinctrl@1c20800 {
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x01c20800 0x400>;
clocks = <&ccu 45>, <&osc24M>, <&osc16Md512>;
clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc16Md512>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
@ -247,8 +249,8 @@ spdif: spdif@1c21000 {
"allwinner,sun8i-h3-spdif";
reg = <0x01c21000 0x400>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu 44>, <&ccu 76>;
resets = <&ccu 32>;
clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
resets = <&ccu RST_BUS_SPDIF>;
clock-names = "apb", "spdif";
dmas = <&dma 2>;
dma-names = "tx";
@ -263,8 +265,8 @@ uart0: serial@01c28000 {
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu 53>;
resets = <&ccu 40>;
clocks = <&ccu CLK_BUS_UART0>;
resets = <&ccu RST_BUS_UART0>;
status = "disabled";
};

2
arch/arm/boot/dts/sunxi-h3-h5.dtsi
View File

@ -394,7 +394,7 @@ timer@01c20c00 {
emac: ethernet@1c30000 {
compatible = "allwinner,sun8i-h3-emac";
syscon = <&syscon>;
reg = <0x01c30000 0x104>;
reg = <0x01c30000 0x10000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
resets = <&ccu RST_BUS_EMAC>;

2
arch/arm/boot/dts/tango4-vantage-1172.dts
View File

@ -22,7 +22,7 @@ chosen {
};
&eth0 {
phy-connection-type = "rgmii";
phy-connection-type = "rgmii-id";
phy-handle = <&eth0_phy>;
#address-cells = <1>;
#size-cells = <0>;

4
arch/arm/mach-davinci/board-da850-evm.c
View File

@ -1166,7 +1166,7 @@ static struct tvp514x_platform_data tvp5146_pdata = {
#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
static const struct vpif_input da850_ch0_inputs[] = {
static struct vpif_input da850_ch0_inputs[] = {
{
.input = {
.index = 0,
@ -1181,7 +1181,7 @@ static const struct vpif_input da850_ch0_inputs[] = {
},
};
static const struct vpif_input da850_ch1_inputs[] = {
static struct vpif_input da850_ch1_inputs[] = {
{
.input = {
.index = 0,

9
arch/arm/mach-davinci/clock.c
View File

@ -218,6 +218,15 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
}
EXPORT_SYMBOL(clk_set_parent);
struct clk *clk_get_parent(struct clk *clk)
{
if (!clk)
return NULL;
return clk->parent;
}
EXPORT_SYMBOL(clk_get_parent);
int clk_register(struct clk *clk)
{
if (clk == NULL || IS_ERR(clk))

20
arch/arm/mach-ep93xx/clock.c
View File

@ -475,6 +475,26 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
}
EXPORT_SYMBOL(clk_set_rate);
long clk_round_rate(struct clk *clk, unsigned long rate)
{
WARN_ON(clk);
return 0;
}
EXPORT_SYMBOL(clk_round_rate);
int clk_set_parent(struct clk *clk, struct clk *parent)
{
WARN_ON(clk);
return 0;
}
EXPORT_SYMBOL(clk_set_parent);
struct clk *clk_get_parent(struct clk *clk)
{
return clk->parent;
}
EXPORT_SYMBOL(clk_get_parent);
static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };

34
arch/arm/mach-ixp4xx/include/mach/io.h
View File

@ -95,8 +95,10 @@ static inline void __indirect_writeb(u8 value, volatile void __iomem *p)
}
static inline void __indirect_writesb(volatile void __iomem *bus_addr,
const u8 *vaddr, int count)
const void *p, int count)
{
const u8 *vaddr = p;
while (count--)
writeb(*vaddr++, bus_addr);
}
@ -118,8 +120,10 @@ static inline void __indirect_writew(u16 value, volatile void __iomem *p)
}
static inline void __indirect_writesw(volatile void __iomem *bus_addr,
const u16 *vaddr, int count)
const void *p, int count)
{
const u16 *vaddr = p;
while (count--)
writew(*vaddr++, bus_addr);
}
@ -137,8 +141,9 @@ static inline void __indirect_writel(u32 value, volatile void __iomem *p)
}
static inline void __indirect_writesl(volatile void __iomem *bus_addr,
const u32 *vaddr, int count)
const void *p, int count)
{
const u32 *vaddr = p;
while (count--)
writel(*vaddr++, bus_addr);
}
@ -160,8 +165,10 @@ static inline u8 __indirect_readb(const volatile void __iomem *p)
}
static inline void __indirect_readsb(const volatile void __iomem *bus_addr,
u8 *vaddr, u32 count)
void *p, u32 count)
{
u8 *vaddr = p;
while (count--)
*vaddr++ = readb(bus_addr);
}
@ -183,8 +190,10 @@ static inline u16 __indirect_readw(const volatile void __iomem *p)
}
static inline void __indirect_readsw(const volatile void __iomem *bus_addr,
u16 *vaddr, u32 count)
void *p, u32 count)
{
u16 *vaddr = p;
while (count--)
*vaddr++ = readw(bus_addr);
}
@ -204,8 +213,10 @@ static inline u32 __indirect_readl(const volatile void __iomem *p)
}
static inline void __indirect_readsl(const volatile void __iomem *bus_addr,
u32 *vaddr, u32 count)
void *p, u32 count)
{
u32 *vaddr = p;
while (count--)
*vaddr++ = readl(bus_addr);
}
@ -523,8 +534,15 @@ static inline void iowrite32_rep(void __iomem *addr, const void *vaddr,
#endif
}
#define ioport_map(port, nr) ((void __iomem*)(port + PIO_OFFSET))
#define ioport_unmap(addr)
#define ioport_map(port, nr) ioport_map(port, nr)
static inline void __iomem *ioport_map(unsigned long port, unsigned int nr)
{
return ((void __iomem*)((port) + PIO_OFFSET));
}
#define ioport_unmap(addr) ioport_unmap(addr)
static inline void ioport_unmap(void __iomem *addr)
{
}
#endif /* CONFIG_PCI */
#endif /* __ASM_ARM_ARCH_IO_H */

2
arch/arm/mach-mmp/devices.c
View File

@ -238,7 +238,7 @@ void pxa_usb_phy_deinit(void __iomem *phy_reg)
#endif
#if IS_ENABLED(CONFIG_USB_SUPPORT)
static u64 usb_dma_mask = ~(u32)0;
static u64 __maybe_unused usb_dma_mask = ~(u32)0;
#if IS_ENABLED(CONFIG_USB_MV_UDC)
struct resource pxa168_u2o_resources[] = {

2
arch/arm/mach-mvebu/platsmp.c
View File

@ -211,7 +211,7 @@ static int mv98dx3236_resume_set_cpu_boot_addr(int hw_cpu, void *boot_addr)
return PTR_ERR(base);
writel(0, base + MV98DX3236_CPU_RESUME_CTRL_REG);
writel(virt_to_phys(boot_addr), base + MV98DX3236_CPU_RESUME_ADDR_REG);
writel(__pa_symbol(boot_addr), base + MV98DX3236_CPU_RESUME_ADDR_REG);
iounmap(base);

12
arch/arm/mach-omap1/board-ams-delta.c
View File

@ -510,6 +510,7 @@ static void __init ams_delta_init(void)
static void modem_pm(struct uart_port *port, unsigned int state, unsigned old)
{
struct modem_private_data *priv = port->private_data;
int ret;
if (IS_ERR(priv->regulator))
return;
@ -518,9 +519,16 @@ static void modem_pm(struct uart_port *port, unsigned int state, unsigned old)
return;
if (state == 0)
regulator_enable(priv->regulator);
ret = regulator_enable(priv->regulator);
else if (old == 0)
regulator_disable(priv->regulator);
ret = regulator_disable(priv->regulator);
else
ret = 0;
if (ret)
dev_warn(port->dev,
"ams_delta modem_pm: failed to %sable regulator: %d\n",
state ? "dis" : "en", ret);
}
static struct plat_serial8250_port ams_delta_modem_ports[] = {

4
arch/arm/mach-omap1/board-osk.c
View File

@ -441,13 +441,11 @@ static struct spi_board_info __initdata mistral_boardinfo[] = { {
.chip_select = 0,
} };
#ifdef CONFIG_PM
static irqreturn_t
osk_mistral_wake_interrupt(int irq, void *ignored)
{
return IRQ_HANDLED;
}
#endif
static void __init osk_mistral_init(void)
{
@ -515,7 +513,6 @@ static void __init osk_mistral_init(void)
gpio_direction_input(OMAP_MPUIO(2));
irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
#ifdef CONFIG_PM
/* share the IRQ in case someone wants to use the
* button for more than wakeup from system sleep.
*/
@ -529,7 +526,6 @@ static void __init osk_mistral_init(void)
ret);
} else
enable_irq_wake(irq);
#endif
} else
printk(KERN_ERR "OSK+Mistral: wakeup button is awol\n");

2
arch/arm/mach-omap2/board-generic.c
View File

@ -28,7 +28,7 @@ static const struct of_device_id omap_dt_match_table[] __initconst = {
{ }
};
static void __init omap_generic_init(void)
static void __init __maybe_unused omap_generic_init(void)
{
pdata_quirks_init(omap_dt_match_table);

2
arch/arm/mach-omap2/io.c
View File

@ -410,7 +410,7 @@ static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
}
static void __init omap_hwmod_init_postsetup(void)
static void __init __maybe_unused omap_hwmod_init_postsetup(void)
{
u8 postsetup_state;

1
arch/arm/mach-omap2/pm34xx.c
View File

@ -486,7 +486,6 @@ int __init omap3_pm_init(void)
ret = request_irq(omap_prcm_event_to_irq("io"),
_prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io",
omap3_pm_init);
enable_irq(omap_prcm_event_to_irq("io"));
if (ret) {
pr_err("pm: Failed to request pm_io irq\n");

7
arch/arm/mach-omap2/prm3xxx.c
View File

@ -692,7 +692,6 @@ static int omap3xxx_prm_late_init(void)
{
struct device_node *np;
int irq_num;
int ret;
if (!(prm_features & PRM_HAS_IO_WAKEUP))
return 0;
@ -712,12 +711,8 @@ static int omap3xxx_prm_late_init(void)
}
omap3xxx_prm_enable_io_wakeup();
ret = omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
if (!ret)
irq_set_status_flags(omap_prcm_event_to_irq("io"),
IRQ_NOAUTOEN);
return ret;
return omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
}
static void __exit omap3xxx_prm_exit(void)

55
arch/arm/mach-omap2/prm44xx.c
View File

@ -336,6 +336,27 @@ static void omap44xx_prm_reconfigure_io_chain(void)
return;
}
/**
* omap44xx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches
*
* Activates the I/O wakeup event latches and allows events logged by
* those latches to signal a wakeup event to the PRCM. For I/O wakeups
* to occur, WAKEUPENABLE bits must be set in the pad mux registers, and
* omap44xx_prm_reconfigure_io_chain() must be called. No return value.
*/
static void __init omap44xx_prm_enable_io_wakeup(void)
{
s32 inst = omap4_prmst_get_prm_dev_inst();
if (inst == PRM_INSTANCE_UNKNOWN)
return;
omap4_prm_rmw_inst_reg_bits(OMAP4430_GLOBAL_WUEN_MASK,
OMAP4430_GLOBAL_WUEN_MASK,
inst,
omap4_prcm_irq_setup.pm_ctrl);
}
/**
* omap44xx_prm_read_reset_sources - return the last SoC reset source
*
@ -668,6 +689,8 @@ struct pwrdm_ops omap4_pwrdm_operations = {
.pwrdm_has_voltdm = omap4_check_vcvp,
};
static int omap44xx_prm_late_init(void);
/*
* XXX document
*/
@ -675,6 +698,7 @@ static struct prm_ll_data omap44xx_prm_ll_data = {
.read_reset_sources = &omap44xx_prm_read_reset_sources,
.was_any_context_lost_old = &omap44xx_prm_was_any_context_lost_old,
.clear_context_loss_flags_old = &omap44xx_prm_clear_context_loss_flags_old,
.late_init = &omap44xx_prm_late_init,
.assert_hardreset = omap4_prminst_assert_hardreset,
.deassert_hardreset = omap4_prminst_deassert_hardreset,
.is_hardreset_asserted = omap4_prminst_is_hardreset_asserted,
@ -711,6 +735,37 @@ int __init omap44xx_prm_init(const struct omap_prcm_init_data *data)
return prm_register(&omap44xx_prm_ll_data);
}
static int omap44xx_prm_late_init(void)
{
int irq_num;
if (!(prm_features & PRM_HAS_IO_WAKEUP))
return 0;
irq_num = of_irq_get(prm_init_data->np, 0);
/*
* Already have OMAP4 IRQ num. For all other platforms, we need
* IRQ numbers from DT
*/
if (irq_num < 0 && !(prm_init_data->flags & PRM_IRQ_DEFAULT)) {
if (irq_num == -EPROBE_DEFER)
return irq_num;
/* Have nothing to do */
return 0;
}
/* Once OMAP4 DT is filled as well */
if (irq_num >= 0) {
omap4_prcm_irq_setup.irq = irq_num;
omap4_prcm_irq_setup.xlate_irq = NULL;
}
omap44xx_prm_enable_io_wakeup();
return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
}
static void __exit omap44xx_prm_exit(void)
{
prm_unregister(&omap44xx_prm_ll_data);

2
arch/arm/mach-prima2/common.c
View File

@ -15,7 +15,7 @@
#include <linux/of_platform.h>
#include "common.h"
static void __init sirfsoc_init_late(void)
static void __init __maybe_unused sirfsoc_init_late(void)
{
sirfsoc_pm_init();
}

1
arch/arm/mach-pxa/Kconfig
View File

@ -566,6 +566,7 @@ config MACH_ICONTROL
config ARCH_PXA_ESERIES
bool "PXA based Toshiba e-series PDAs"
select FB_W100
select FB
select PXA25x
config MACH_E330

10
arch/arm/mach-pxa/include/mach/mtd-xip.h
View File

@ -17,11 +17,15 @@
#include <mach/regs-ost.h>
#define xip_irqpending() (ICIP & ICMR)
/* restored July 2017, this did not build since 2011! */
#define ICIP io_p2v(0x40d00000)
#define ICMR io_p2v(0x40d00004)
#define xip_irqpending() (readl(ICIP) & readl(ICMR))
/* we sample OSCR and convert desired delta to usec (1/4 ~= 1000000/3686400) */
#define xip_currtime() (OSCR)
#define xip_elapsed_since(x) (signed)((OSCR - (x)) / 4)
#define xip_currtime() readl(OSCR)
#define xip_elapsed_since(x) (signed)((readl(OSCR) - (x)) / 4)
/*
* xip_cpu_idle() is used when waiting for a delay equal or larger than

4
arch/arm/mach-rpc/include/mach/hardware.h
View File

@ -25,8 +25,8 @@
* *_SIZE is the size of the region
* *_BASE is the virtual address
*/
#define RAM_SIZE 0x10000000
#define RAM_START 0x10000000
#define RPC_RAM_SIZE 0x10000000
#define RPC_RAM_START 0x10000000
#define EASI_SIZE 0x08000000 /* EASI I/O */
#define EASI_START 0x08000000

25
arch/arm/mach-sa1100/clock.c
View File

@ -35,6 +35,31 @@ struct clk clk_##_name = { \
static DEFINE_SPINLOCK(clocks_lock);
/* Dummy clk routine to build generic kernel parts that may be using them */
long clk_round_rate(struct clk *clk, unsigned long rate)
{
return clk_get_rate(clk);
}
EXPORT_SYMBOL(clk_round_rate);
int clk_set_rate(struct clk *clk, unsigned long rate)
{
return 0;
}
EXPORT_SYMBOL(clk_set_rate);
int clk_set_parent(struct clk *clk, struct clk *parent)
{
return 0;
}
EXPORT_SYMBOL(clk_set_parent);
struct clk *clk_get_parent(struct clk *clk)
{
return NULL;
}
EXPORT_SYMBOL(clk_get_parent);
static void clk_gpio27_enable(struct clk *clk)
{
/*

4
arch/arm/mach-sa1100/include/mach/mtd-xip.h
View File

@ -20,7 +20,7 @@
#define xip_irqpending() (ICIP & ICMR)
/* we sample OSCR and convert desired delta to usec (1/4 ~= 1000000/3686400) */
#define xip_currtime() (OSCR)
#define xip_elapsed_since(x) (signed)((OSCR - (x)) / 4)
#define xip_currtime() readl_relaxed(OSCR)
#define xip_elapsed_since(x) (signed)((readl_relaxed(OSCR) - (x)) / 4)
#endif /* __ARCH_SA1100_MTD_XIP_H__ */

6
arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c
View File

@ -67,8 +67,12 @@ static int regulator_quirk_notify(struct notifier_block *nb,
{
struct device *dev = data;
struct i2c_client *client;
static bool done;
u32 mon;
if (done)
return 0;
mon = ioread32(irqc + IRQC_MONITOR);
dev_dbg(dev, "%s: %ld, IRQC_MONITOR = 0x%x\n", __func__, action, mon);
if (mon & REGULATOR_IRQ_MASK)
@ -99,7 +103,7 @@ static int regulator_quirk_notify(struct notifier_block *nb,
remove:
dev_info(dev, "IRQ2 is not asserted, removing quirk\n");
bus_unregister_notifier(&i2c_bus_type, nb);
done = true;
iounmap(irqc);
return 0;
}

29
arch/arm/mach-w90x900/clock.c
View File

@ -93,3 +93,32 @@ void nuc900_subclk_enable(struct clk *clk, int enable)
__raw_writel(clken, W90X900_VA_CLKPWR + SUBCLK);
}
/* dummy functions, should not be called */
long clk_round_rate(struct clk *clk, unsigned long rate)
{
WARN_ON(clk);
return 0;
}
EXPORT_SYMBOL(clk_round_rate);
int clk_set_rate(struct clk *clk, unsigned long rate)
{
WARN_ON(clk);
return 0;
}
EXPORT_SYMBOL(clk_set_rate);
int clk_set_parent(struct clk *clk, struct clk *parent)
{
WARN_ON(clk);
return 0;
}
EXPORT_SYMBOL(clk_set_parent);
struct clk *clk_get_parent(struct clk *clk)
{
WARN_ON(clk);
return NULL;
}
EXPORT_SYMBOL(clk_get_parent);

2
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
View File

@ -452,7 +452,7 @@ i2c2: i2c@1c2b400 {
emac: ethernet@1c30000 {
compatible = "allwinner,sun50i-a64-emac";
syscon = <&syscon>;
reg = <0x01c30000 0x100>;
reg = <0x01c30000 0x10000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
resets = <&ccu RST_BUS_EMAC>;

2
arch/arm64/boot/dts/amlogic/meson-gx.dtsi
View File

@ -400,7 +400,7 @@ i2c_AO: i2c@500 {
};
pwm_AO_ab: pwm@550 {
compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
compatible = "amlogic,meson-gx-ao-pwm", "amlogic,meson-gxbb-ao-pwm";
reg = <0x0 0x00550 0x0 0x10>;
#pwm-cells = <3>;
status = "disabled";

4
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
View File

@ -109,8 +109,8 @@ &pwm_AO_ab {
status = "okay";
pinctrl-0 = <&pwm_ao_a_3_pins>, <&pwm_ao_b_pins>;
pinctrl-names = "default";
clocks = <&clkc CLKID_FCLK_DIV4>;
clock-names = "clkin0";
clocks = <&xtal> , <&xtal>;
clock-names = "clkin0", "clkin1" ;
};
&pwm_ef {

103
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
View File

@ -10,12 +10,20 @@
#include <dt-bindings/input/input.h>
#include "meson-gxl-s905x-p212.dtsi"
#include "meson-gxl-s905x.dtsi"
/ {
compatible = "libretech,cc", "amlogic,s905x", "amlogic,meson-gxl";
model = "Libre Technology CC";
aliases {
serial0 = &uart_AO;
};
chosen {
stdout-path = "serial0:115200n8";
};
cvbs-connector {
compatible = "composite-video-connector";
@ -26,6 +34,11 @@ cvbs_connector_in: endpoint {
};
};
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
@ -53,6 +66,39 @@ blue {
linux,default-trigger = "heartbeat";
};
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
vcc_3v3: regulator-vcc_3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vcc_card: regulator-vcc-card {
compatible = "regulator-gpio";
regulator-name = "VCC_CARD";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
gpios-states = <0>;
states = <3300000 0>,
<1800000 1>;
};
vddio_boot: regulator-vddio_boot {
compatible = "regulator-fixed";
regulator-name = "VDDIO_BOOT";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&cvbs_vdac_port {
@ -61,6 +107,16 @@ cvbs_vdac_out: endpoint {
};
};
&ethmac {
status = "okay";
};
&ir {
status = "okay";
pinctrl-0 = <&remote_input_ao_pins>;
pinctrl-names = "default";
};
&hdmi_tx {
status = "okay";
pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
@ -73,20 +129,43 @@ hdmi_tx_tmds_out: endpoint {
};
};
/*
* The following devices exists but are exposed on the general
* purpose GPIO header. End user may well decide to use those pins
* for another purpose
*/
/* SD card */
&sd_emmc_b {
status = "okay";
pinctrl-0 = <&sdcard_pins>;
pinctrl-names = "default";
&sd_emmc_a {
status = "disabled";
bus-width = <4>;
cap-sd-highspeed;
max-frequency = <100000000>;
disable-wp;
cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
cd-inverted;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vcc_card>;
};
&uart_A {
status = "disabled";
/* eMMC */
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>;
pinctrl-names = "default";
bus-width = <8>;
cap-mmc-highspeed;
max-frequency = <50000000>;
non-removable;
disable-wp;
mmc-pwrseq = <&emmc_pwrseq>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vddio_boot>;
};
&wifi32k {
status = "disabled";
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};

2
arch/arm64/boot/dts/marvell/armada-37xx.dtsi
View File

@ -219,7 +219,7 @@ pinctrl_sb: pinctrl@18800 {
reg = <0x18800 0x100>, <0x18C00 0x20>;
gpiosb: gpio {
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_sb 0 0 29>;
gpio-ranges = <&pinctrl_sb 0 0 30>;
gpio-controller;
interrupts =
<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,

1
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
View File

@ -270,6 +270,7 @@ cpm_crypto: crypto@800000 {
interrupt-names = "mem", "ring0", "ring1",
"ring2", "ring3", "eip";
clocks = <&cpm_clk 1 26>;
dma-coherent;
};
};

3
arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
View File

@ -64,7 +64,7 @@ cps_rtc: rtc@284000 {
compatible = "marvell,armada-8k-rtc";
reg = <0x284000 0x20>, <0x284080 0x24>;
reg-names = "rtc", "rtc-soc";
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
};
cps_ethernet: ethernet@0 {
@ -261,6 +261,7 @@ cps_crypto: crypto@800000 {
interrupt-names = "mem", "ring0", "ring1",
"ring2", "ring3", "eip";
clocks = <&cps_clk 1 26>;
dma-coherent;
/*
* The cryptographic engine found on the cp110
* master is enabled by default at the SoC

2
arch/arm64/boot/dts/renesas/salvator-common.dtsi
View File

@ -508,7 +508,7 @@ &rcar_sound {
/* audio_clkout0/1/2/3 */
#clock-cells = <1>;
clock-frequency = <11289600 12288000>;
clock-frequency = <12288000 11289600>;
status = "okay";

2
arch/arm64/boot/dts/renesas/ulcb.dtsi
View File

@ -281,7 +281,7 @@ &rcar_sound {
/* audio_clkout0/1/2/3 */
#clock-cells = <1>;
clock-frequency = <11289600 12288000>;
clock-frequency = <12288000 11289600>;
status = "okay";

1
arch/arm64/configs/defconfig
View File

@ -476,6 +476,7 @@ CONFIG_QCOM_CLK_SMD_RPM=y
CONFIG_MSM_GCC_8916=y
CONFIG_MSM_GCC_8994=y
CONFIG_MSM_MMCC_8996=y
CONFIG_HWSPINLOCK=y
CONFIG_HWSPINLOCK_QCOM=y
CONFIG_ARM_MHU=y
CONFIG_PLATFORM_MHU=y

14
drivers/bus/uniphier-system-bus.c
View File

@ -256,10 +256,23 @@ static int uniphier_system_bus_probe(struct platform_device *pdev)
uniphier_system_bus_set_reg(priv);
platform_set_drvdata(pdev, priv);
/* Now, the bus is configured. Populate platform_devices below it */
return of_platform_default_populate(dev->of_node, NULL, dev);
}
static int __maybe_unused uniphier_system_bus_resume(struct device *dev)
{
uniphier_system_bus_set_reg(dev_get_drvdata(dev));
return 0;
}
static const struct dev_pm_ops uniphier_system_bus_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(NULL, uniphier_system_bus_resume)
};
static const struct of_device_id uniphier_system_bus_match[] = {
{ .compatible = "socionext,uniphier-system-bus" },
{ /* sentinel */ }
@ -271,6 +284,7 @@ static struct platform_driver uniphier_system_bus_driver = {
.driver = {
.name = "uniphier-system-bus",
.of_match_table = uniphier_system_bus_match,
.pm = &uniphier_system_bus_pm_ops,
},
};
module_platform_driver(uniphier_system_bus_driver);

1
drivers/soc/zte/Kconfig
View File

@ -2,6 +2,7 @@
# ZTE SoC drivers
#
menuconfig SOC_ZTE
depends on ARCH_ZX || COMPILE_TEST
bool "ZTE SoC driver support"
if SOC_ZTE