From 3003cfa147e7626d26f6adae819380db600b7fd7 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Fri, 29 Jun 2018 10:20:27 +0800 Subject: [PATCH 01/14] phy: phy-mtk-tphy: use SPDX license tag Use SPDX-License-Identifier tag instead of the GPL license text Signed-off-by: Chunfeng Yun Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/mediatek/Makefile | 1 + drivers/phy/mediatek/phy-mtk-tphy.c | 10 +--------- 2 files changed, 2 insertions(+), 9 deletions(-) diff --git a/drivers/phy/mediatek/Makefile b/drivers/phy/mediatek/Makefile index e5074b607d3d..ee49edc97ee9 100644 --- a/drivers/phy/mediatek/Makefile +++ b/drivers/phy/mediatek/Makefile @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 # # Makefile for the phy drivers. # diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c index 38c281b5abbb..b962339074ba 100644 --- a/drivers/phy/mediatek/phy-mtk-tphy.c +++ b/drivers/phy/mediatek/phy-mtk-tphy.c @@ -1,16 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2015 MediaTek Inc. * Author: Chunfeng Yun * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * */ #include From 8ccba47c699f82cb7b5f6bf24ffe6cd1d5c53381 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Fri, 29 Jun 2018 10:20:28 +0800 Subject: [PATCH 02/14] dt-bindings: phy-mtk-tphy: add optional properties for u2phy Add some optional properties for eye diagram test and BC12 of u2phy Signed-off-by: Chunfeng Yun Reviewed-by: Rob Herring Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt index 0d34b2b4a6b7..a5f7a4f0dbc1 100644 --- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt +++ b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt @@ -47,6 +47,12 @@ Required properties (port (child) node): - PHY_TYPE_PCIE - PHY_TYPE_SATA +Optional properties (PHY_TYPE_USB2 port (child) node): +- mediatek,eye-src : u32, the value of slew rate calibrate +- mediatek,eye-vrt : u32, the selection of VRT reference voltage +- mediatek,eye-term : u32, the selection of HS_TX TERM reference voltage +- mediatek,bc12 : bool, enable BC12 of u2phy if support it + Example: u3phy: usb-phy@11290000 { From 8158e917d91cb0be7e6177a7e839fcbb89d63867 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Fri, 29 Jun 2018 10:20:29 +0800 Subject: [PATCH 03/14] phy: phy-mtk-tphy: add properties for eye diagram test Add properties for Eye diagram test of HQA which sometimes need adjust some parameters of u2phy Signed-off-by: Chunfeng Yun Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/mediatek/phy-mtk-tphy.c | 62 +++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c index b962339074ba..9ab6f2e73c58 100644 --- a/drivers/phy/mediatek/phy-mtk-tphy.c +++ b/drivers/phy/mediatek/phy-mtk-tphy.c @@ -42,6 +42,12 @@ #define PA0_RG_U2PLL_FORCE_ON BIT(15) #define PA0_RG_USB20_INTR_EN BIT(5) +#define U3P_USBPHYACR1 0x004 +#define PA1_RG_VRT_SEL GENMASK(14, 12) +#define PA1_RG_VRT_SEL_VAL(x) ((0x7 & (x)) << 12) +#define PA1_RG_TERM_SEL GENMASK(10, 8) +#define PA1_RG_TERM_SEL_VAL(x) ((0x7 & (x)) << 8) + #define U3P_USBPHYACR2 0x008 #define PA2_RG_SIF_U2PLL_FORCE_EN BIT(18) @@ -288,6 +294,9 @@ struct mtk_phy_instance { struct clk *ref_clk; /* reference clock of anolog phy */ u32 index; u8 type; + int eye_src; + int eye_vrt; + int eye_term; }; struct mtk_tphy { @@ -312,6 +321,10 @@ static void hs_slew_rate_calibrate(struct mtk_tphy *tphy, int fm_out; u32 tmp; + /* use force value */ + if (instance->eye_src) + return; + /* enable USB ring oscillator */ tmp = readl(com + U3P_USBPHYACR5); tmp |= PA5_RG_U2_HSTX_SRCAL_EN; @@ -818,6 +831,52 @@ static void phy_v2_banks_init(struct mtk_tphy *tphy, } } +static void phy_parse_property(struct mtk_tphy *tphy, + struct mtk_phy_instance *instance) +{ + struct device *dev = &instance->phy->dev; + + if (instance->type != PHY_TYPE_USB2) + return; + + device_property_read_u32(dev, "mediatek,eye-src", + &instance->eye_src); + device_property_read_u32(dev, "mediatek,eye-vrt", + &instance->eye_vrt); + device_property_read_u32(dev, "mediatek,eye-term", + &instance->eye_term); +} + +static void u2_phy_props_set(struct mtk_tphy *tphy, + struct mtk_phy_instance *instance) +{ + struct u2phy_banks *u2_banks = &instance->u2_banks; + void __iomem *com = u2_banks->com; + u32 tmp; + + + if (instance->eye_src) { + tmp = readl(com + U3P_USBPHYACR5); + tmp &= ~PA5_RG_U2_HSTX_SRCTRL; + tmp |= PA5_RG_U2_HSTX_SRCTRL_VAL(instance->eye_src); + writel(tmp, com + U3P_USBPHYACR5); + } + + if (instance->eye_vrt) { + tmp = readl(com + U3P_USBPHYACR1); + tmp &= ~PA1_RG_VRT_SEL; + tmp |= PA1_RG_VRT_SEL_VAL(instance->eye_vrt); + writel(tmp, com + U3P_USBPHYACR1); + } + + if (instance->eye_term) { + tmp = readl(com + U3P_USBPHYACR1); + tmp &= ~PA1_RG_TERM_SEL; + tmp |= PA1_RG_TERM_SEL_VAL(instance->eye_term); + writel(tmp, com + U3P_USBPHYACR1); + } +} + static int mtk_phy_init(struct phy *phy) { struct mtk_phy_instance *instance = phy_get_drvdata(phy); @@ -839,6 +898,7 @@ static int mtk_phy_init(struct phy *phy) switch (instance->type) { case PHY_TYPE_USB2: u2_phy_instance_init(tphy, instance); + u2_phy_props_set(tphy, instance); break; case PHY_TYPE_USB3: u3_phy_instance_init(tphy, instance); @@ -951,6 +1011,8 @@ static struct phy *mtk_phy_xlate(struct device *dev, return ERR_PTR(-EINVAL); } + phy_parse_property(tphy, instance); + return instance->phy; } From d4f97f10dac48bf49a199b826c3e8f1c4798bea2 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Fri, 29 Jun 2018 10:20:30 +0800 Subject: [PATCH 04/14] phy: phy-mtk-tphy: add property for BC12 Some platforms support BC12 which is disabled by default, here add a property to enable it if need Signed-off-by: Chunfeng Yun Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/mediatek/phy-mtk-tphy.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c index 9ab6f2e73c58..3eb8e1bd7b78 100644 --- a/drivers/phy/mediatek/phy-mtk-tphy.c +++ b/drivers/phy/mediatek/phy-mtk-tphy.c @@ -101,6 +101,9 @@ #define P2C_RG_AVALID BIT(2) #define P2C_RG_IDDIG BIT(1) +#define U3P_U2PHYBC12C 0x080 +#define P2C_RG_CHGDT_EN BIT(0) + #define U3P_U3_CHIP_GPIO_CTLD 0x0c #define P3C_REG_IP_SW_RST BIT(31) #define P3C_MCU_BUS_CK_GATE_EN BIT(30) @@ -297,6 +300,7 @@ struct mtk_phy_instance { int eye_src; int eye_vrt; int eye_term; + bool bc12_en; }; struct mtk_tphy { @@ -839,12 +843,16 @@ static void phy_parse_property(struct mtk_tphy *tphy, if (instance->type != PHY_TYPE_USB2) return; + instance->bc12_en = device_property_read_bool(dev, "mediatek,bc12"); device_property_read_u32(dev, "mediatek,eye-src", &instance->eye_src); device_property_read_u32(dev, "mediatek,eye-vrt", &instance->eye_vrt); device_property_read_u32(dev, "mediatek,eye-term", &instance->eye_term); + dev_dbg(dev, "bc12:%d, src:%d, vrt:%d, term:%d\n", + instance->bc12_en, instance->eye_src, + instance->eye_vrt, instance->eye_term); } static void u2_phy_props_set(struct mtk_tphy *tphy, @@ -854,6 +862,11 @@ static void u2_phy_props_set(struct mtk_tphy *tphy, void __iomem *com = u2_banks->com; u32 tmp; + if (instance->bc12_en) { + tmp = readl(com + U3P_U2PHYBC12C); + tmp |= P2C_RG_CHGDT_EN; /* BC1.2 path Enable */ + writel(tmp, com + U3P_U2PHYBC12C); + } if (instance->eye_src) { tmp = readl(com + U3P_USBPHYACR5); From 5b9d2e8fb5fcb0e671994ce458d5d3e6221670af Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Fri, 29 Jun 2018 10:20:31 +0800 Subject: [PATCH 05/14] MAINTAINERS: update files of MediaTek USB3 PHYs Update maintained files include MediaTek USB3 PHYs drivers and their bindings Signed-off-by: Chunfeng Yun Signed-off-by: Kishon Vijay Abraham I --- MAINTAINERS | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 9d5eeff51b5f..2b782f1d1bc0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1647,7 +1647,8 @@ M: Chunfeng Yun L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) S: Maintained -F: drivers/phy/mediatek/phy-mtk-tphy.c +F: drivers/phy/mediatek/ +F: Documentation/devicetree/bindings/phy/phy-mtk-* ARM/MICREL KS8695 ARCHITECTURE M: Greg Ungerer From 95fb21253ea56d330053bafcf3cb502171551253 Mon Sep 17 00:00:00 2001 From: Ray Jui Date: Fri, 6 Jul 2018 17:18:32 -0700 Subject: [PATCH 06/14] dt-bindings: phy: Add binding doc for Stingray PCIe PHY Add binding document for Stingray PCIe PHYs for both PAXB and PAXC based root complex Signed-off-by: Ray Jui Reviewed-by: Rob Herring Signed-off-by: Kishon Vijay Abraham I --- .../bindings/phy/brcm,sr-pcie-phy.txt | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/brcm,sr-pcie-phy.txt diff --git a/Documentation/devicetree/bindings/phy/brcm,sr-pcie-phy.txt b/Documentation/devicetree/bindings/phy/brcm,sr-pcie-phy.txt new file mode 100644 index 000000000000..e8d82286beb9 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/brcm,sr-pcie-phy.txt @@ -0,0 +1,41 @@ +Broadcom Stingray PCIe PHY + +Required properties: +- compatible: must be "brcm,sr-pcie-phy" +- reg: base address and length of the PCIe SS register space +- brcm,sr-cdru: phandle to the CDRU syscon node +- brcm,sr-mhb: phandle to the MHB syscon node +- #phy-cells: Must be 1, denotes the PHY index + +For PAXB based root complex, one can have a configuration of up to 8 PHYs +PHY index goes from 0 to 7 + +For the internal PAXC based root complex, PHY index is always 8 + +Example: + mhb: syscon@60401000 { + compatible = "brcm,sr-mhb", "syscon"; + reg = <0 0x60401000 0 0x38c>; + }; + + cdru: syscon@6641d000 { + compatible = "brcm,sr-cdru", "syscon"; + reg = <0 0x6641d000 0 0x400>; + }; + + pcie_phy: phy@40000000 { + compatible = "brcm,sr-pcie-phy"; + reg = <0 0x40000000 0 0x800>; + brcm,sr-cdru = <&cdru>; + brcm,sr-mhb = <&mhb>; + #phy-cells = <1>; + }; + + /* users of the PCIe PHY */ + + pcie0: pcie@48000000 { + ... + ... + phys = <&pcie_phy 0>; + phy-names = "pcie-phy"; + }; From 92696a89cd3f9c878182c00cae60fb7a0056cc30 Mon Sep 17 00:00:00 2001 From: Ray Jui Date: Fri, 6 Jul 2018 17:18:33 -0700 Subject: [PATCH 07/14] phy: bcm-sr-pcie: Add Stingray PCIe PHY driver Add Stingray PCIe PHY driver for both PAXB and PAXC root complex Signed-off-by: Ray Jui Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/broadcom/Kconfig | 10 + drivers/phy/broadcom/Makefile | 2 + drivers/phy/broadcom/phy-bcm-sr-pcie.c | 305 +++++++++++++++++++++++++ 3 files changed, 317 insertions(+) create mode 100644 drivers/phy/broadcom/phy-bcm-sr-pcie.c diff --git a/drivers/phy/broadcom/Kconfig b/drivers/phy/broadcom/Kconfig index 97d27b0d5cc7..8786a9674471 100644 --- a/drivers/phy/broadcom/Kconfig +++ b/drivers/phy/broadcom/Kconfig @@ -80,3 +80,13 @@ config PHY_BRCM_USB This driver is required by the USB XHCI, EHCI and OHCI drivers. If unsure, say N. + +config PHY_BCM_SR_PCIE + tristate "Broadcom Stingray PCIe PHY driver" + depends on OF && (ARCH_BCM_IPROC || COMPILE_TEST) + select GENERIC_PHY + select MFD_SYSCON + default ARCH_BCM_IPROC + help + Enable this to support the Broadcom Stingray PCIe PHY + If unsure, say N. diff --git a/drivers/phy/broadcom/Makefile b/drivers/phy/broadcom/Makefile index 13e000c1a43a..0f60184e6662 100644 --- a/drivers/phy/broadcom/Makefile +++ b/drivers/phy/broadcom/Makefile @@ -9,3 +9,5 @@ obj-$(CONFIG_PHY_BRCM_SATA) += phy-brcm-sata.o obj-$(CONFIG_PHY_BRCM_USB) += phy-brcm-usb-dvr.o phy-brcm-usb-dvr-objs := phy-brcm-usb.o phy-brcm-usb-init.o + +obj-$(CONFIG_PHY_BCM_SR_PCIE) += phy-bcm-sr-pcie.o diff --git a/drivers/phy/broadcom/phy-bcm-sr-pcie.c b/drivers/phy/broadcom/phy-bcm-sr-pcie.c new file mode 100644 index 000000000000..c10e95f86de5 --- /dev/null +++ b/drivers/phy/broadcom/phy-bcm-sr-pcie.c @@ -0,0 +1,305 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016-2018 Broadcom + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* we have up to 8 PAXB based RC. The 9th one is always PAXC */ +#define SR_NR_PCIE_PHYS 9 +#define SR_PAXC_PHY_IDX (SR_NR_PCIE_PHYS - 1) + +#define PCIE_PIPEMUX_CFG_OFFSET 0x10c +#define PCIE_PIPEMUX_SELECT_STRAP 0xf + +#define CDRU_STRAP_DATA_LSW_OFFSET 0x5c +#define PCIE_PIPEMUX_SHIFT 19 +#define PCIE_PIPEMUX_MASK 0xf + +#define MHB_MEM_PW_PAXC_OFFSET 0x1c0 +#define MHB_PWR_ARR_POWERON 0x8 +#define MHB_PWR_ARR_POWEROK 0x4 +#define MHB_PWR_POWERON 0x2 +#define MHB_PWR_POWEROK 0x1 +#define MHB_PWR_STATUS_MASK (MHB_PWR_ARR_POWERON | \ + MHB_PWR_ARR_POWEROK | \ + MHB_PWR_POWERON | \ + MHB_PWR_POWEROK) + +struct sr_pcie_phy_core; + +/** + * struct sr_pcie_phy - Stingray PCIe PHY + * + * @core: pointer to the Stingray PCIe PHY core control + * @index: PHY index + * @phy: pointer to the kernel PHY device + */ +struct sr_pcie_phy { + struct sr_pcie_phy_core *core; + unsigned int index; + struct phy *phy; +}; + +/** + * struct sr_pcie_phy_core - Stingray PCIe PHY core control + * + * @dev: pointer to device + * @base: base register of PCIe SS + * @cdru: regmap to the CDRU device + * @mhb: regmap to the MHB device + * @pipemux: pipemuex strap + * @phys: array of PCIe PHYs + */ +struct sr_pcie_phy_core { + struct device *dev; + void __iomem *base; + struct regmap *cdru; + struct regmap *mhb; + u32 pipemux; + struct sr_pcie_phy phys[SR_NR_PCIE_PHYS]; +}; + +/* + * PCIe PIPEMUX lookup table + * + * Each array index represents a PIPEMUX strap setting + * The array element represents a bitmap where a set bit means the PCIe + * core and associated serdes has been enabled as RC and is available for use + */ +static const u8 pipemux_table[] = { + /* PIPEMUX = 0, EP 1x16 */ + 0x00, + /* PIPEMUX = 1, EP 2x8 */ + 0x00, + /* PIPEMUX = 2, EP 4x4 */ + 0x00, + /* PIPEMUX = 3, RC 2x8, cores 0, 7 */ + 0x81, + /* PIPEMUX = 4, RC 4x4, cores 0, 1, 6, 7 */ + 0xc3, + /* PIPEMUX = 5, RC 8x2, all 8 cores */ + 0xff, + /* PIPEMUX = 6, RC 3x4 + 2x2, cores 0, 2, 3, 6, 7 */ + 0xcd, + /* PIPEMUX = 7, RC 1x4 + 6x2, cores 0, 2, 3, 4, 5, 6, 7 */ + 0xfd, + /* PIPEMUX = 8, EP 1x8 + RC 4x2, cores 4, 5, 6, 7 */ + 0xf0, + /* PIPEMUX = 9, EP 1x8 + RC 2x4, cores 6, 7 */ + 0xc0, + /* PIPEMUX = 10, EP 2x4 + RC 2x4, cores 1, 6 */ + 0x42, + /* PIPEMUX = 11, EP 2x4 + RC 4x2, cores 2, 3, 4, 5 */ + 0x3c, + /* PIPEMUX = 12, EP 1x4 + RC 6x2, cores 2, 3, 4, 5, 6, 7 */ + 0xfc, + /* PIPEMUX = 13, RC 2x4 + RC 1x4 + 2x2, cores 2, 3, 6 */ + 0x4c, +}; + +/* + * Return true if the strap setting is valid + */ +static bool pipemux_strap_is_valid(u32 pipemux) +{ + return !!(pipemux < ARRAY_SIZE(pipemux_table)); +} + +/* + * Read the PCIe PIPEMUX from strap + */ +static u32 pipemux_strap_read(struct sr_pcie_phy_core *core) +{ + u32 pipemux; + + /* + * Read PIPEMUX configuration register to determine the pipemux setting + * + * In the case when the value indicates using HW strap, fall back to + * use HW strap + */ + pipemux = readl(core->base + PCIE_PIPEMUX_CFG_OFFSET); + pipemux &= PCIE_PIPEMUX_MASK; + if (pipemux == PCIE_PIPEMUX_SELECT_STRAP) { + regmap_read(core->cdru, CDRU_STRAP_DATA_LSW_OFFSET, &pipemux); + pipemux >>= PCIE_PIPEMUX_SHIFT; + pipemux &= PCIE_PIPEMUX_MASK; + } + + return pipemux; +} + +/* + * Given a PIPEMUX strap and PCIe core index, this function returns true if the + * PCIe core needs to be enabled + */ +static bool pcie_core_is_for_rc(struct sr_pcie_phy *phy) +{ + struct sr_pcie_phy_core *core = phy->core; + unsigned int core_idx = phy->index; + + return !!((pipemux_table[core->pipemux] >> core_idx) & 0x1); +} + +static int sr_pcie_phy_init(struct phy *p) +{ + struct sr_pcie_phy *phy = phy_get_drvdata(p); + + /* + * Check whether this PHY is for root complex or not. If yes, return + * zero so the host driver can proceed to enumeration. If not, return + * an error and that will force the host driver to bail out + */ + if (pcie_core_is_for_rc(phy)) + return 0; + + return -ENODEV; +} + +static int sr_paxc_phy_init(struct phy *p) +{ + struct sr_pcie_phy *phy = phy_get_drvdata(p); + struct sr_pcie_phy_core *core = phy->core; + unsigned int core_idx = phy->index; + u32 val; + + if (core_idx != SR_PAXC_PHY_IDX) + return -EINVAL; + + regmap_read(core->mhb, MHB_MEM_PW_PAXC_OFFSET, &val); + if ((val & MHB_PWR_STATUS_MASK) != MHB_PWR_STATUS_MASK) { + dev_err(core->dev, "PAXC is not powered up\n"); + return -ENODEV; + } + + return 0; +} + +static const struct phy_ops sr_pcie_phy_ops = { + .init = sr_pcie_phy_init, + .owner = THIS_MODULE, +}; + +static const struct phy_ops sr_paxc_phy_ops = { + .init = sr_paxc_phy_init, + .owner = THIS_MODULE, +}; + +static struct phy *sr_pcie_phy_xlate(struct device *dev, + struct of_phandle_args *args) +{ + struct sr_pcie_phy_core *core; + int phy_idx; + + core = dev_get_drvdata(dev); + if (!core) + return ERR_PTR(-EINVAL); + + phy_idx = args->args[0]; + + if (WARN_ON(phy_idx >= SR_NR_PCIE_PHYS)) + return ERR_PTR(-ENODEV); + + return core->phys[phy_idx].phy; +} + +static int sr_pcie_phy_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *node = dev->of_node; + struct sr_pcie_phy_core *core; + struct resource *res; + struct phy_provider *provider; + unsigned int phy_idx = 0; + + core = devm_kzalloc(dev, sizeof(*core), GFP_KERNEL); + if (!core) + return -ENOMEM; + + core->dev = dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + core->base = devm_ioremap_resource(core->dev, res); + if (IS_ERR(core->base)) + return PTR_ERR(core->base); + + core->cdru = syscon_regmap_lookup_by_phandle(node, "brcm,sr-cdru"); + if (IS_ERR(core->cdru)) { + dev_err(core->dev, "unable to find CDRU device\n"); + return PTR_ERR(core->cdru); + } + + core->mhb = syscon_regmap_lookup_by_phandle(node, "brcm,sr-mhb"); + if (IS_ERR(core->mhb)) { + dev_err(core->dev, "unable to find MHB device\n"); + return PTR_ERR(core->mhb); + } + + /* read the PCIe PIPEMUX strap setting */ + core->pipemux = pipemux_strap_read(core); + if (!pipemux_strap_is_valid(core->pipemux)) { + dev_err(core->dev, "invalid PCIe PIPEMUX strap %u\n", + core->pipemux); + return -EIO; + } + + for (phy_idx = 0; phy_idx < SR_NR_PCIE_PHYS; phy_idx++) { + struct sr_pcie_phy *p = &core->phys[phy_idx]; + const struct phy_ops *ops; + + if (phy_idx == SR_PAXC_PHY_IDX) + ops = &sr_paxc_phy_ops; + else + ops = &sr_pcie_phy_ops; + + p->phy = devm_phy_create(dev, NULL, ops); + if (IS_ERR(p->phy)) { + dev_err(dev, "failed to create PCIe PHY\n"); + return PTR_ERR(p->phy); + } + + p->core = core; + p->index = phy_idx; + phy_set_drvdata(p->phy, p); + } + + dev_set_drvdata(dev, core); + + provider = devm_of_phy_provider_register(dev, sr_pcie_phy_xlate); + if (IS_ERR(provider)) { + dev_err(dev, "failed to register PHY provider\n"); + return PTR_ERR(provider); + } + + dev_info(dev, "Stingray PCIe PHY driver initialized\n"); + + return 0; +} + +static const struct of_device_id sr_pcie_phy_match_table[] = { + { .compatible = "brcm,sr-pcie-phy" }, + { } +}; +MODULE_DEVICE_TABLE(of, sr_pcie_phy_match_table); + +static struct platform_driver sr_pcie_phy_driver = { + .driver = { + .name = "sr-pcie-phy", + .of_match_table = sr_pcie_phy_match_table, + }, + .probe = sr_pcie_phy_probe, +}; +module_platform_driver(sr_pcie_phy_driver); + +MODULE_AUTHOR("Ray Jui "); +MODULE_DESCRIPTION("Broadcom Stingray PCIe PHY driver"); +MODULE_LICENSE("GPL v2"); From 8b1087fa3a272c962836ea0e9a8bba14b0ee0ee5 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Fri, 6 Jul 2018 16:31:42 -0700 Subject: [PATCH 08/14] phy: qcom-qmp: Fix dts bindings to reflect reality A few patches have landed for the qcom-qmp PHY that affect how you would write a device tree node. ...yet the bindings weren't updated. Let's remedy the situation and make the bindings refelect reality. Fixes: efb05a50c956 ("phy: qcom-qmp: Add support for QMP V3 USB3 PHY") Fixes: ac0d239936bd ("phy: qcom-qmp: Add support for runtime PM") Signed-off-by: Douglas Anderson Signed-off-by: Kishon Vijay Abraham I --- .../devicetree/bindings/phy/qcom-qmp-phy.txt | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt index 266a1bb8bb6e..0c7629e88bf3 100644 --- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt @@ -12,7 +12,14 @@ Required properties: "qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845, "qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845. - - reg: offset and length of register set for PHY's common serdes block. + - reg: + - For "qcom,sdm845-qmp-usb3-phy": + - index 0: address and length of register set for PHY's common serdes + block. + - named register "dp_com" (using reg-names): address and length of the + DP_COM control block. + - For all others: + - offset and length of register set for PHY's common serdes block. - #clock-cells: must be 1 - Phy pll outputs a bunch of clocks for Tx, Rx and Pipe @@ -60,7 +67,10 @@ Required nodes: Required properties for child node: - reg: list of offset and length pairs of register sets for PHY blocks - - tx, rx and pcs. + - index 0: tx + - index 1: rx + - index 2: pcs + - index 3: pcs_misc (optional) - #phy-cells: must be 0 From 01abdcc5288f3bf3ea65378a4717138508b9c574 Mon Sep 17 00:00:00 2001 From: "Gustavo A. R. Silva" Date: Thu, 5 Jul 2018 10:00:09 -0500 Subject: [PATCH 09/14] phy: qcom-usb-hs: Mark expected switch fall-through In preparation to enabling -Wimplicit-fallthrough, mark switch cases where we are expecting to fall through. Signed-off-by: Gustavo A. R. Silva Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/qualcomm/phy-qcom-usb-hs.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/phy/qualcomm/phy-qcom-usb-hs.c b/drivers/phy/qualcomm/phy-qcom-usb-hs.c index 2d0c70b5589f..abbbe75070da 100644 --- a/drivers/phy/qualcomm/phy-qcom-usb-hs.c +++ b/drivers/phy/qualcomm/phy-qcom-usb-hs.c @@ -55,6 +55,7 @@ static int qcom_usb_hs_phy_set_mode(struct phy *phy, enum phy_mode mode) case PHY_MODE_USB_OTG: case PHY_MODE_USB_HOST: val |= ULPI_INT_IDGRD; + /* fall through */ case PHY_MODE_USB_DEVICE: val |= ULPI_INT_SESS_VALID; default: From 4fa88cd3370ed33119863747a4db7f5e3f1dc308 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sun, 10 Jun 2018 21:22:46 +0300 Subject: [PATCH 10/14] dt-bindings: phy: Renesas R-Car Gen3 PCIe PHY bindings This PHY is still mostly undocumented -- the only documented registers exist on R-Car V3H (R8A77980) SoC. Add the corresponding device tree bindings. Signed-off-by: Sergei Shtylyov Reviewed-by: Simon Horman Reviewed-by: Rob Herring Signed-off-by: Kishon Vijay Abraham I --- .../bindings/phy/rcar-gen3-phy-pcie.txt | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/rcar-gen3-phy-pcie.txt diff --git a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-pcie.txt b/Documentation/devicetree/bindings/phy/rcar-gen3-phy-pcie.txt new file mode 100644 index 000000000000..63853b35e083 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/rcar-gen3-phy-pcie.txt @@ -0,0 +1,24 @@ +* Renesas R-Car generation 3 PCIe PHY + +This file provides information on what the device node for the R-Car +generation 3 PCIe PHY contains. + +Required properties: +- compatible: "renesas,r8a77980-pcie-phy" if the device is a part of the + R8A77980 SoC. +- reg: offset and length of the register block. +- clocks: clock phandle and specifier pair. +- power-domains: power domain phandle and specifier pair. +- resets: reset phandle and specifier pair. +- #phy-cells: see phy-bindings.txt in the same directory, must be <0>. + +Example (R-Car V3H): + + pcie-phy@e65d0000 { + compatible = "renesas,r8a77980-pcie-phy"; + reg = <0 0xe65d0000 0 0x8000>; + #phy-cells = <0>; + clocks = <&cpg CPG_MOD 319>; + power-domains = <&sysc 32>; + resets = <&cpg 319>; + }; From 2ce7f2f425ef7464a2a9a872d2e9acad49e6cb3e Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sun, 10 Jun 2018 21:24:13 +0300 Subject: [PATCH 11/14] phy: Renesas R-Car gen3 PCIe PHY driver This PHY is still mostly undocumented -- the only documented registers exist on R-Car V3H (R8A77980) SoC where this PHY stays in a powered-down state after a reset and thus we must power it up for PCIe to work... Signed-off-by: Sergei Shtylyov Reviewed-by: Simon Horman Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/renesas/Kconfig | 7 ++ drivers/phy/renesas/Makefile | 1 + drivers/phy/renesas/phy-rcar-gen3-pcie.c | 151 +++++++++++++++++++++++ 3 files changed, 159 insertions(+) create mode 100644 drivers/phy/renesas/phy-rcar-gen3-pcie.c diff --git a/drivers/phy/renesas/Kconfig b/drivers/phy/renesas/Kconfig index c845facacb06..4bd390c79d21 100644 --- a/drivers/phy/renesas/Kconfig +++ b/drivers/phy/renesas/Kconfig @@ -8,6 +8,13 @@ config PHY_RCAR_GEN2 help Support for USB PHY found on Renesas R-Car generation 2 SoCs. +config PHY_RCAR_GEN3_PCIE + tristate "Renesas R-Car generation 3 PCIe PHY driver" + depends on ARCH_RENESAS + select GENERIC_PHY + help + Support for the PCIe PHY found on Renesas R-Car generation 3 SoCs. + config PHY_RCAR_GEN3_USB2 tristate "Renesas R-Car generation 3 USB 2.0 PHY driver" depends on ARCH_RENESAS diff --git a/drivers/phy/renesas/Makefile b/drivers/phy/renesas/Makefile index 8b6025916a93..4b76fc439ed6 100644 --- a/drivers/phy/renesas/Makefile +++ b/drivers/phy/renesas/Makefile @@ -1,3 +1,4 @@ obj-$(CONFIG_PHY_RCAR_GEN2) += phy-rcar-gen2.o +obj-$(CONFIG_PHY_RCAR_GEN3_PCIE) += phy-rcar-gen3-pcie.o obj-$(CONFIG_PHY_RCAR_GEN3_USB2) += phy-rcar-gen3-usb2.o obj-$(CONFIG_PHY_RCAR_GEN3_USB3) += phy-rcar-gen3-usb3.o diff --git a/drivers/phy/renesas/phy-rcar-gen3-pcie.c b/drivers/phy/renesas/phy-rcar-gen3-pcie.c new file mode 100644 index 000000000000..c4e4aa216936 --- /dev/null +++ b/drivers/phy/renesas/phy-rcar-gen3-pcie.c @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas R-Car Gen3 PCIe PHY driver + * + * Copyright (C) 2018 Cogent Embedded, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define PHY_CTRL 0x4000 /* R8A77980 only */ + +/* PHY control register (PHY_CTRL) */ +#define PHY_CTRL_PHY_PWDN BIT(2) + +struct rcar_gen3_phy { + struct phy *phy; + spinlock_t lock; + void __iomem *base; +}; + +static void rcar_gen3_phy_pcie_modify_reg(struct phy *p, unsigned int reg, + u32 clear, u32 set) +{ + struct rcar_gen3_phy *phy = phy_get_drvdata(p); + void __iomem *base = phy->base; + unsigned long flags; + u32 value; + + spin_lock_irqsave(&phy->lock, flags); + + value = readl(base + reg); + value &= ~clear; + value |= set; + writel(value, base + reg); + + spin_unlock_irqrestore(&phy->lock, flags); +} + +static int r8a77980_phy_pcie_power_on(struct phy *p) +{ + /* Power on the PCIe PHY */ + rcar_gen3_phy_pcie_modify_reg(p, PHY_CTRL, PHY_CTRL_PHY_PWDN, 0); + + return 0; +} + +static int r8a77980_phy_pcie_power_off(struct phy *p) +{ + /* Power off the PCIe PHY */ + rcar_gen3_phy_pcie_modify_reg(p, PHY_CTRL, 0, PHY_CTRL_PHY_PWDN); + + return 0; +} + +static const struct phy_ops r8a77980_phy_pcie_ops = { + .power_on = r8a77980_phy_pcie_power_on, + .power_off = r8a77980_phy_pcie_power_off, + .owner = THIS_MODULE, +}; + +static const struct of_device_id rcar_gen3_phy_pcie_match_table[] = { + { .compatible = "renesas,r8a77980-pcie-phy" }, + { } +}; +MODULE_DEVICE_TABLE(of, rcar_gen3_phy_pcie_match_table); + +static int rcar_gen3_phy_pcie_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct phy_provider *provider; + struct rcar_gen3_phy *phy; + struct resource *res; + void __iomem *base; + int error; + + if (!dev->of_node) { + dev_err(dev, + "This driver must only be instantiated from the device tree\n"); + return -EINVAL; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); + if (!phy) + return -ENOMEM; + + spin_lock_init(&phy->lock); + + phy->base = base; + + /* + * devm_phy_create() will call pm_runtime_enable(&phy->dev); + * And then, phy-core will manage runtime PM for this device. + */ + pm_runtime_enable(dev); + + phy->phy = devm_phy_create(dev, NULL, &r8a77980_phy_pcie_ops); + if (IS_ERR(phy->phy)) { + dev_err(dev, "Failed to create PCIe PHY\n"); + error = PTR_ERR(phy->phy); + goto error; + } + phy_set_drvdata(phy->phy, phy); + + provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + if (IS_ERR(provider)) { + dev_err(dev, "Failed to register PHY provider\n"); + error = PTR_ERR(provider); + goto error; + } + + return 0; + +error: + pm_runtime_disable(dev); + + return error; +} + +static int rcar_gen3_phy_pcie_remove(struct platform_device *pdev) +{ + pm_runtime_disable(&pdev->dev); + + return 0; +}; + +static struct platform_driver rcar_gen3_phy_driver = { + .driver = { + .name = "phy_rcar_gen3_pcie", + .of_match_table = rcar_gen3_phy_pcie_match_table, + }, + .probe = rcar_gen3_phy_pcie_probe, + .remove = rcar_gen3_phy_pcie_remove, +}; + +module_platform_driver(rcar_gen3_phy_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Renesas R-Car Gen3 PCIe PHY"); +MODULE_AUTHOR("Sergei Shtylyov "); From d5f5ee1a16a4f14e9b98d1352bc850e43f2968ca Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Wed, 16 May 2018 15:48:57 +0800 Subject: [PATCH 12/14] phy: berlin: switch to SPDX license identifier Use the appropriate SPDX license identifier and drop the previous license text. Signed-off-by: Jisheng Zhang Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/marvell/phy-berlin-sata.c | 5 +---- drivers/phy/marvell/phy-berlin-usb.c | 5 +---- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/drivers/phy/marvell/phy-berlin-sata.c b/drivers/phy/marvell/phy-berlin-sata.c index 2c7a57f2d595..c1bb6725e48f 100644 --- a/drivers/phy/marvell/phy-berlin-sata.c +++ b/drivers/phy/marvell/phy-berlin-sata.c @@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Marvell Berlin SATA PHY driver * * Copyright (C) 2014 Marvell Technology Group Ltd. * * Antoine Ténart - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ #include diff --git a/drivers/phy/marvell/phy-berlin-usb.c b/drivers/phy/marvell/phy-berlin-usb.c index 8f2b5cae360f..a43df63007c5 100644 --- a/drivers/phy/marvell/phy-berlin-usb.c +++ b/drivers/phy/marvell/phy-berlin-usb.c @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2014 Marvell Technology Group Ltd. * * Antoine Tenart * Jisheng Zhang - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ #include From 5a78671309e029d8e3427a5b9ec440c0d9ba9bde Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Wed, 6 Jun 2018 15:42:28 +0900 Subject: [PATCH 13/14] dt-bindings: rcar-gen3-phy-usb2: Add bindings for r8a77990 This patch adds suuport for r8a77990 (R-Car E3). Signed-off-by: Yoshihiro Shimoda Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt b/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt index dbd137c079e2..fb4a204da2bf 100644 --- a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt +++ b/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt @@ -10,6 +10,8 @@ Required properties: SoC. "renesas,usb2-phy-r8a77965" if the device is a part of an R8A77965 SoC. + "renesas,usb2-phy-r8a77990" if the device is a part of an + R8A77990 SoC. "renesas,usb2-phy-r8a77995" if the device is a part of an R8A77995 SoC. "renesas,rcar-gen3-usb2-phy" for a generic R-Car Gen3 compatible device. From ec14b83a1ee40a9a72d84f0af356eccc948b24c4 Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Fri, 13 Jul 2018 16:53:10 +0200 Subject: [PATCH 14/14] phy: mvebu-cp110-comphy: switch to SPDX identifier Use the appropriate SPDX license identifier and drop the license text. This patch is only cosmetic. Signed-off-by: Antoine Tenart Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c index 4ef429250d7b..86a5f7b9448b 100644 --- a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c +++ b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2017 Marvell * * Antoine Tenart - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ #include