pinctrl: aspeed-g5: Delay acquisition of regmaps
While sorting out some devicetree issues I found that the pinctrl driver
was failing to acquire its GFX regmap even though the phandle was
present in the devicetree:
[ 0.124190] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: No GFX phandle found, some mux configurations may fail
Without access to the GFX regmap we fail to configure the mux for the
VPO function:
[ 1.548866] pinctrl core: add 1 pinctrl maps
[ 1.549826] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: found group selector 164 for VPO
[ 1.550638] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 144 (V20) for 1e6e6000.display
[ 1.551346] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 145 (U19) for 1e6e6000.display
...
[ 1.562057] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 218 (T22) for 1e6e6000.display
[ 1.562541] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 219 (R20) for 1e6e6000.display
[ 1.563113] Muxing pin 144 for VPO
[ 1.563456] Want SCU8C[0x00000001]=0x1, got 0x0 from 0x00000000
[ 1.564624] aspeed_gfx 1e6e6000.display: Error applying setting, reverse things back
This turned out to be a simple problem of timing: The ASPEED pinctrl
driver is probed during arch_initcall(), while GFX is processed much
later. As such the GFX syscon is not yet registered during the pinctrl
probe() and we get an -EPROBE_DEFER when we try to look it up, however
we must not defer probing the pinctrl driver for the inability to mux
some GFX-related functions.
Switch to lazily grabbing the regmaps when they're first required by the
mux configuration. This generates a bit of noise in the patch as we have
to drop the `const` qualifier on arguments for several function
prototypes, but has the benefit of working.
I've smoke tested this for the ast2500-evb under qemu with a dummy
graphics device. We now succeed in our attempts to configure the SoC's
VPO pinmux function.
Fixes: 7d29ed88ac
("pinctrl: aspeed: Read and write bits in LPC and GFX controllers")
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20190724080155.12209-1-andrew@aj.id.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
parent
5f9e832c13
commit
674fa8daa8
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@ -2412,7 +2412,7 @@ static const struct aspeed_pin_config aspeed_g4_configs[] = {
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{ PIN_CONFIG_INPUT_DEBOUNCE, { C14, B14 }, SCUA8, 27 },
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{ PIN_CONFIG_INPUT_DEBOUNCE, { C14, B14 }, SCUA8, 27 },
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};
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};
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static int aspeed_g4_sig_expr_set(const struct aspeed_pinmux_data *ctx,
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static int aspeed_g4_sig_expr_set(struct aspeed_pinmux_data *ctx,
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const struct aspeed_sig_expr *expr,
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const struct aspeed_sig_expr *expr,
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bool enable)
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bool enable)
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{
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{
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@ -2507,6 +2507,61 @@ static struct aspeed_pin_config aspeed_g5_configs[] = {
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{ PIN_CONFIG_INPUT_DEBOUNCE, { A20, B19 }, SCUA8, 27 },
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{ PIN_CONFIG_INPUT_DEBOUNCE, { A20, B19 }, SCUA8, 27 },
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};
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};
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static struct regmap *aspeed_g5_acquire_regmap(struct aspeed_pinmux_data *ctx,
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int ip)
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{
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if (ip == ASPEED_IP_SCU) {
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WARN(!ctx->maps[ip], "Missing SCU syscon!");
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return ctx->maps[ip];
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}
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if (ip >= ASPEED_NR_PINMUX_IPS)
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return ERR_PTR(-EINVAL);
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if (likely(ctx->maps[ip]))
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return ctx->maps[ip];
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if (ip == ASPEED_IP_GFX) {
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struct device_node *node;
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struct regmap *map;
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node = of_parse_phandle(ctx->dev->of_node,
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"aspeed,external-nodes", 0);
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if (node) {
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map = syscon_node_to_regmap(node);
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of_node_put(node);
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if (IS_ERR(map))
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return map;
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} else
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return ERR_PTR(-ENODEV);
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ctx->maps[ASPEED_IP_GFX] = map;
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dev_dbg(ctx->dev, "Acquired GFX regmap");
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return map;
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}
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if (ip == ASPEED_IP_LPC) {
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struct device_node *node;
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struct regmap *map;
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node = of_parse_phandle(ctx->dev->of_node,
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"aspeed,external-nodes", 1);
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if (node) {
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map = syscon_node_to_regmap(node->parent);
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of_node_put(node);
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if (IS_ERR(map))
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return map;
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} else
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map = ERR_PTR(-ENODEV);
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ctx->maps[ASPEED_IP_LPC] = map;
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dev_dbg(ctx->dev, "Acquired LPC regmap");
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return map;
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}
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return ERR_PTR(-EINVAL);
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}
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/**
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/**
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* Configure a pin's signal by applying an expression's descriptor state for
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* Configure a pin's signal by applying an expression's descriptor state for
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* all descriptors in the expression.
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* all descriptors in the expression.
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@ -2520,7 +2575,7 @@ static struct aspeed_pin_config aspeed_g5_configs[] = {
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* Return: 0 if the expression is configured as requested and a negative error
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* Return: 0 if the expression is configured as requested and a negative error
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* code otherwise
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* code otherwise
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*/
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*/
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static int aspeed_g5_sig_expr_set(const struct aspeed_pinmux_data *ctx,
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static int aspeed_g5_sig_expr_set(struct aspeed_pinmux_data *ctx,
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const struct aspeed_sig_expr *expr,
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const struct aspeed_sig_expr *expr,
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bool enable)
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bool enable)
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{
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{
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@ -2531,9 +2586,15 @@ static int aspeed_g5_sig_expr_set(const struct aspeed_pinmux_data *ctx,
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const struct aspeed_sig_desc *desc = &expr->descs[i];
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const struct aspeed_sig_desc *desc = &expr->descs[i];
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u32 pattern = enable ? desc->enable : desc->disable;
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u32 pattern = enable ? desc->enable : desc->disable;
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u32 val = (pattern << __ffs(desc->mask));
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u32 val = (pattern << __ffs(desc->mask));
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struct regmap *map;
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if (!ctx->maps[desc->ip])
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map = aspeed_g5_acquire_regmap(ctx, desc->ip);
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return -ENODEV;
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if (IS_ERR(map)) {
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dev_err(ctx->dev,
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"Failed to acquire regmap for IP block %d\n",
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desc->ip);
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return PTR_ERR(map);
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}
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/*
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/*
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* Strap registers are configured in hardware or by early-boot
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* Strap registers are configured in hardware or by early-boot
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@ -2641,34 +2702,11 @@ static struct pinctrl_desc aspeed_g5_pinctrl_desc = {
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static int aspeed_g5_pinctrl_probe(struct platform_device *pdev)
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static int aspeed_g5_pinctrl_probe(struct platform_device *pdev)
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{
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{
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int i;
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int i;
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struct regmap *map;
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struct device_node *node;
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for (i = 0; i < ARRAY_SIZE(aspeed_g5_pins); i++)
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for (i = 0; i < ARRAY_SIZE(aspeed_g5_pins); i++)
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aspeed_g5_pins[i].number = i;
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aspeed_g5_pins[i].number = i;
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node = of_parse_phandle(pdev->dev.of_node, "aspeed,external-nodes", 0);
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aspeed_g5_pinctrl_data.pinmux.dev = &pdev->dev;
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map = syscon_node_to_regmap(node);
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of_node_put(node);
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if (IS_ERR(map)) {
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dev_warn(&pdev->dev, "No GFX phandle found, some mux configurations may fail\n");
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map = NULL;
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}
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aspeed_g5_pinctrl_data.pinmux.maps[ASPEED_IP_GFX] = map;
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node = of_parse_phandle(pdev->dev.of_node, "aspeed,external-nodes", 1);
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if (node) {
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map = syscon_node_to_regmap(node->parent);
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if (IS_ERR(map)) {
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dev_warn(&pdev->dev, "LHC parent is not a syscon, some mux configurations may fail\n");
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map = NULL;
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}
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} else {
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dev_warn(&pdev->dev, "No LHC phandle found, some mux configurations may fail\n");
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map = NULL;
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}
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of_node_put(node);
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aspeed_g5_pinctrl_data.pinmux.maps[ASPEED_IP_LPC] = map;
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return aspeed_pinctrl_probe(pdev, &aspeed_g5_pinctrl_desc,
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return aspeed_pinctrl_probe(pdev, &aspeed_g5_pinctrl_desc,
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&aspeed_g5_pinctrl_data);
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&aspeed_g5_pinctrl_data);
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@ -71,7 +71,7 @@ int aspeed_pinmux_get_fn_groups(struct pinctrl_dev *pctldev,
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return 0;
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return 0;
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}
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}
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static int aspeed_sig_expr_enable(const struct aspeed_pinmux_data *ctx,
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static int aspeed_sig_expr_enable(struct aspeed_pinmux_data *ctx,
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const struct aspeed_sig_expr *expr)
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const struct aspeed_sig_expr *expr)
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{
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{
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int ret;
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int ret;
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@ -86,7 +86,7 @@ static int aspeed_sig_expr_enable(const struct aspeed_pinmux_data *ctx,
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return 0;
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return 0;
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}
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}
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static int aspeed_sig_expr_disable(const struct aspeed_pinmux_data *ctx,
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static int aspeed_sig_expr_disable(struct aspeed_pinmux_data *ctx,
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const struct aspeed_sig_expr *expr)
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const struct aspeed_sig_expr *expr)
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{
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{
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int ret;
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int ret;
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@ -109,7 +109,7 @@ static int aspeed_sig_expr_disable(const struct aspeed_pinmux_data *ctx,
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*
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*
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* Return: 0 if all expressions are disabled, otherwise a negative error code
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* Return: 0 if all expressions are disabled, otherwise a negative error code
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*/
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*/
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static int aspeed_disable_sig(const struct aspeed_pinmux_data *ctx,
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static int aspeed_disable_sig(struct aspeed_pinmux_data *ctx,
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const struct aspeed_sig_expr **exprs)
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const struct aspeed_sig_expr **exprs)
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{
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{
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int ret = 0;
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int ret = 0;
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@ -217,8 +217,7 @@ int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
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{
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{
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int i;
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int i;
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int ret;
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int ret;
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const struct aspeed_pinctrl_data *pdata =
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struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
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pinctrl_dev_get_drvdata(pctldev);
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const struct aspeed_pin_group *pgroup = &pdata->pinmux.groups[group];
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const struct aspeed_pin_group *pgroup = &pdata->pinmux.groups[group];
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const struct aspeed_pin_function *pfunc =
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const struct aspeed_pin_function *pfunc =
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&pdata->pinmux.functions[function];
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&pdata->pinmux.functions[function];
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@ -306,8 +305,7 @@ int aspeed_gpio_request_enable(struct pinctrl_dev *pctldev,
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unsigned int offset)
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unsigned int offset)
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{
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{
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int ret;
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int ret;
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const struct aspeed_pinctrl_data *pdata =
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struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
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pinctrl_dev_get_drvdata(pctldev);
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const struct aspeed_pin_desc *pdesc = pdata->pins[offset].drv_data;
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const struct aspeed_pin_desc *pdesc = pdata->pins[offset].drv_data;
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const struct aspeed_sig_expr ***prios, **funcs, *expr;
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const struct aspeed_sig_expr ***prios, **funcs, *expr;
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@ -702,11 +702,12 @@ struct aspeed_pin_function {
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struct aspeed_pinmux_data;
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struct aspeed_pinmux_data;
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struct aspeed_pinmux_ops {
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struct aspeed_pinmux_ops {
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int (*set)(const struct aspeed_pinmux_data *ctx,
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int (*set)(struct aspeed_pinmux_data *ctx,
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const struct aspeed_sig_expr *expr, bool enabled);
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const struct aspeed_sig_expr *expr, bool enabled);
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};
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};
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struct aspeed_pinmux_data {
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struct aspeed_pinmux_data {
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struct device *dev;
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struct regmap *maps[ASPEED_NR_PINMUX_IPS];
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struct regmap *maps[ASPEED_NR_PINMUX_IPS];
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const struct aspeed_pinmux_ops *ops;
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const struct aspeed_pinmux_ops *ops;
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@ -725,7 +726,7 @@ int aspeed_sig_expr_eval(const struct aspeed_pinmux_data *ctx,
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const struct aspeed_sig_expr *expr,
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const struct aspeed_sig_expr *expr,
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bool enabled);
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bool enabled);
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static inline int aspeed_sig_expr_set(const struct aspeed_pinmux_data *ctx,
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static inline int aspeed_sig_expr_set(struct aspeed_pinmux_data *ctx,
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const struct aspeed_sig_expr *expr,
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const struct aspeed_sig_expr *expr,
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bool enabled)
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bool enabled)
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{
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{
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