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clk: aspeed: Add 24MHz fixed clock 

Add a 24MHz fixed clock.
This clock will be used for certain devices, e.g. pwm.

Signed-off-by: Lei YU <mine260309@gmail.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Lei YU 2018-05-18 16:57:02 +08:00 committed by Stephen Boyd
parent 60cc43fc88
commit 67b6e5cfdb
2 changed files with 9 additions and 1 deletions
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9
drivers/clk/clk-aspeed.c
View File

@ -14,7 +14,7 @@
#include <dt-bindings/clock/aspeed-clock.h>
#define ASPEED_NUM_CLKS 35
#define ASPEED_NUM_CLKS 36
#define ASPEED_RESET_CTRL 0x04
#define ASPEED_CLK_SELECTION 0x08
@ -474,6 +474,13 @@ static int aspeed_clk_probe(struct platform_device *pdev)
return PTR_ERR(hw);
aspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw;
/* Fixed 24MHz clock */
hw = clk_hw_register_fixed_rate(NULL, "fixed-24m", "clkin",
0, 24000000);
if (IS_ERR(hw))
return PTR_ERR(hw);
aspeed_clk_data->hws[ASPEED_CLK_24M] = hw;
/*
* TODO: There are a number of clocks that not included in this driver
* as more information is required:

1
include/dt-bindings/clock/aspeed-clock.h
View File

@ -38,6 +38,7 @@
#define ASPEED_CLK_MAC 32
#define ASPEED_CLK_BCLK 33
#define ASPEED_CLK_MPLL 34
#define ASPEED_CLK_24M 35
#define ASPEED_RESET_XDMA 0
#define ASPEED_RESET_MCTP 1